Abstract: Embodiments of the present disclosure provide systems and methods for implementing separate and orthogonal impedance tuning (Zcal) and feed forward equalization (FFE) operations of a segmented multiple level source-series terminated (SST) transmitter. An SST transmitter output driver comprising a plurality of parallel-connected output driver slices coupled to a data communication link and a multiple-tap FFE unit comprising at least one pre-cursor tap, main tap or post-cursor tap. The system performs impedance tuning within each of the plurality of parallel-connected output driver slices of the output driver. The system performs FFE resolution on the plurality of parallel-connected output driver slices of the output driver by assigning respective ones of the plurality of parallel-connected output driver slices to a specific FFE tap of the of the at least one pre-cursor tap, main tap or post-cursor tap of the FFE unit.

Abstract: Aspects of the invention include receiving, by a controller, an indication of a chip initialization for a duty cycle correction (DCC) circuit, wherein the duty cycle correction circuit includes a main path including a main multiplexer (MUX) having a first input and a main driver circuit, a replica path including a replica MUX having a second input and a replica driver circuit, a selection MUX connected to the main path and the replica path, operating the selection MUX, during a period for the chip initialization, to select the main path as an input to the selection MUX, inputting a pre-defined data pattern to the main path, comparing an output of the selection MUX with the pre-defined data pattern to determine duty cycle issue, and generating an adjustment vector based on the determined duty cycle issue.

Abstract: Aspects of the invention include receiving, by a controller, an indication of a chip initialization for a duty cycle correction (DCC) circuit, wherein the duty cycle correction circuit includes a main path including a main multiplexer (MUX) having a first input and a main driver circuit, a replica path including a replica MUX having a second input and a replica driver circuit, a selection MUX connected to the main path and the replica path, operating the selection MUX, during a period for the chip initialization, to select the main path as an input to the selection MUX, inputting a pre-defined data pattern to the main path, comparing an output of the selection MUX with the pre-defined data pattern to determine duty cycle issue, and generating an adjustment vector based on the determined duty cycle issue.

Abstract: An Electro-Static Discharge (ESD) protection circuit is disclosed. In some implementations, the ESD protection circuit includes a first ESD diode, a second ESD diode, a passive equalization network and a programmable resistor network. The first ESD diode is coupled to the passive equalization network. The programmable resistor network is coupled between the passive equalization network and the second ESD diode. The programmable resistor network can be programmed to place the ESD protection circuit in one of a plurality of receiver modes based on a type of a transmitter from which the receiver is receiving signals.

Abstract: Clock data recovery broadcast for multi-lane SerDes is disclosed. In some implementations, a serial input/output (I/O) interface includes a master lane and a plurality of slave lanes to receive serial incoming data. The master lane has a master clock and data recovery (CDR) module to generate master data sample clock control signals. The master data sample clock control signals can be broadcasted to the slave lanes. Furthermore, each of the plurality of slave lanes having a slave CDR module. The slave CDR module can include a clock edge tracking module to generate local data sample clock control signals, and a multiplexer to select the master data sample clock control signals or local data sample clock control signals to apply in the respective slave lane in response to a signal from a CDR controller indicative of a low power mode.

Abstract: Clock data recovery broadcast for multi-lane SerDes is disclosed. In some implementations, a serial input/output (I/O) interface includes a master lane and a plurality of slave lanes to receive serial incoming data. The master lane has a master clock and data recovery (CDR) module to generate master data sample clock control signals. The master data sample clock control signals can be broadcasted to the slave lanes. Furthermore, each of the plurality of slave lanes having a slave CDR module. The slave CDR module can include a clock edge tracking module to generate local data sample clock control signals, and a multiplexer to select the master data sample clock control signals or local data sample clock control signals to apply in the respective slave lane in response to a signal from a CDR controller indicative of a low power mode.

Abstract: An Electro-Static Discharge (ESD) protection circuit is disclosed. In some implementations, the ESD protection circuit includes a first ESD diode, a second ESD diode, a passive equalization network and a programmable resistor network. The first ESD diode is coupled to the passive equalization network. The programmable resistor network is coupled between the passive equalization network and the second ESD diode. The programmable resistor network can be programmed to place the ESD protection circuit in one of a plurality of receiver modes based on a type of a transmitter from which the receiver is receiving signals.

Abstract: Systems and methods to provide a low-power mode for serial links are disclosed. One embodiment of such a system includes a transmitter coupled to a link; a receiver coupled to the link and configured to receive signals over the link from the transmitter; a transmit control module configured to cause the transmitter to enter and exit a low-power mode; and a clock module coupled to the transmitter and configured to provide a clock signal to the transmitter, wherein the clock module is further configured to provide the clock signal as a divided clock signal to the transmitter when the transmitter is in the low-power mode, further wherein the divided clock signal has a same phase as the clock signal before entry into the low-power mode.

Abstract: Systems and methods to provide a low-power mode for serial links are disclosed. One embodiment of such a system includes a transmitter coupled to a link; a receiver coupled to the link and configured to receive signals over the link from the transmitter; a transmit control module configured to cause the transmitter to enter and exit a low-power mode; and a clock module coupled to the transmitter and configured to provide a clock signal to the transmitter, wherein the clock module is further configured to provide the clock signal as a divided clock signal to the transmitter when the transmitter is in the low-power mode, further wherein the divided clock signal has a same phase as the clock signal before entry into the low-power mode.

Abstract: A system is disclosed. The system includes a first circuit, the first circuit includes a bias device for allowing the first circuit to transition between a first mode and a second mode. The system further includes a second circuit which controls the bias device. The second circuit provides a bias voltage at a sub-threshold voltage level to the bias device when the first device is in one of the first and the second mode. The second circuit provides a bias voltage at a threshold voltage level or higher when the first device is in one of the first and the second mode. Accordingly, the transition time between modes of the first circuit is minimized.