Patents by Inventor Carroll C. Speir
Carroll C. Speir has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230198506Abstract: Systems, devices, and methods related to a sample rate converter (SRC) for implementing a rate conversion R are provided. The SRC receives input samples at an input rate Fin and outputs samples at an output rate Fout=Fin×R, where R is a fractional value greater than 1. The SRC includes a plurality of filters to process the received input samples and a multiplier-adder block to generate the output samples based on respective delta values and outputs of the plurality of filters. The SRC further includes a plurality of buffers to buffer samples between the plurality of filters and the multiplier-adder block based at least in part on N buffer read pointers, where N is an integer greater than 1. The SRC further includes resampler control circuitry to generate N delta values of the delta values and the N buffer read pointers in parallel based on R.Type: ApplicationFiled: August 9, 2022Publication date: June 22, 2023Applicant: Analog Devices International Unlimited CompanyInventors: Devendra PONNAPUREDDY, Carroll C. SPEIR
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Patent number: 11057125Abstract: Various approaches to implementing digital loopback in a radio frequency (RF) system are disclosed. An example RF system includes a receiver that includes an ADC and a transmitter that includes a DAC. The apparatus includes multiple digital loopback circuits provided at different points between the digital domain processing of the receiver and the transmitter. Each digital loopback circuit may include a combiner and one or more weighing circuits, which make the circuit programmable. The combiner of a given digital loopback circuit is configured to combine a RX signal and a TX signal at a particular point of the digital domain processing of the receiver and the transmitter where said digital loopback circuit is implemented. The one or more weighting circuits are configured to define the how much of the TX signal and/or RX signal is used for said combination.Type: GrantFiled: June 25, 2020Date of Patent: July 6, 2021Assignee: ANALOG DEVICES, INC.Inventors: Peter Delos, Carroll C. Speir
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Patent number: 10727842Abstract: Aspects of this disclosure relate to adjusting a phase of a clock signal provided to a device based on a feedback signal from the device. The feedback signal can provide phase information associated with the device and/or other information associated with the device, such as temperature information. A feedback signal processor can compute a phase control signal based on the feedback signal. The phase control signal can be used to adjust the phase of the clock signal. By adjusting the phase of one or more clock signals, several devices, such as data converters, can be synchronized.Type: GrantFiled: May 21, 2019Date of Patent: July 28, 2020Assignee: Analog Devices, Inc.Inventors: John Kevin Behel, Kenny Gentile, Carroll C. Speir, Matthew D. McShea, Matthew Louis Courcy, Reuben Pascal Nelson
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Patent number: 10720904Abstract: A sample rate converter (“SRC”) for implementing a rate conversion L/M is described wherein data is input to the SRC at an input rate (“Fin”) and output from the SRC at an output rate (“Fout”) equal to Fin*L/M. The SRC includes a low pass filter (“LPF”) including P multiply-add instances, wherein P is a parallelization factor of the SRC; an input formatter for arranging samples received at the SRC in accordance with the rate conversion L/M and providing P*Tpp input samples to the filter at a given time, wherein Tpp is a number of taps per phase of the LPF; and a coefficient bank for storing a plurality of coefficients and for providing P*Tpp of the coefficients to the LPF at a given time.Type: GrantFiled: November 12, 2018Date of Patent: July 21, 2020Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANYInventors: Vinoth Kumar, Bhanu Pande, Carroll C. Speir, Satishchandra G. Rao, Sajkapoor P. K.
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Publication number: 20200153415Abstract: A sample rate converter (“SRC”) for implementing a rate conversion L/M is described wherein data is input to the SRC at an input rate (“Fin”) and output from the SRC at an output rate (“Fout”) equal to Fin*L/M. The SRC includes a low pass filter (“LPF”) including P multiply-add instances, wherein P is a parallelization factor of the SRC; an input formatter for arranging samples received at the SRC in accordance with the rate conversion L/M and providing P*Tpp input samples to the filter at a given time, wherein Tpp is a number of taps per phase of the LPF; and a coefficient bank for storing a plurality of coefficients and for providing P*Tpp of the coefficients to the LPF at a given time.Type: ApplicationFiled: November 12, 2018Publication date: May 14, 2020Applicant: Analog Devices International Unlimited CompanyInventors: Vinoth Kumar, Bhanu Pande, Carroll C. SPEIR, Satishchandra G. RAO, Sajkapoor P. K.
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Publication number: 20190341922Abstract: Aspects of this disclosure relate to adjusting a phase of a clock signal provided to a device based on a feedback signal from the device. The feedback signal can provide phase information associated with the device and/or other information associated with the device, such as temperature information. A feedback signal processor can compute a phase control signal based on the feedback signal. The phase control signal can be used to adjust the phase of the clock signal. By adjusting the phase of one or more clock signals, several devices, such as data converters, can be synchronized.Type: ApplicationFiled: May 21, 2019Publication date: November 7, 2019Inventors: John Kevin Behel, Kenny Gentile, Carroll C. Speir, Matthew D. McShea, Matthew Louis Courcy, Reuben Pascal Nelson
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Patent number: 10454483Abstract: A time-to-digital converter (TDC) detects a timing relationship between signals representing two temporal events. Several samples are acquired over a certain time period for each event, and the signals related to the different events are digitized or quantized either by separate TDCs or by a single TDC in a time-sequential manner. The quantized results are then processed, for example added to/subtracted from one another, and used to determine the phase or time difference between the two events. When information being quantized is quasi-static over time periods where the measurement is performed, the instantaneous or “one shot” accuracy of a TDC need not be as good as or better than the desired time resolution. Digitally processing the signals and averaging the results moves an otherwise difficult analog quantizer problem to the digital domain where savings in power and chip area can be easily achieved without sacrificing accuracy.Type: GrantFiled: October 24, 2016Date of Patent: October 22, 2019Assignee: ANALOG DEVICES, INC.Inventors: Ralph D. Moore, Ryan Lee Bunch, Carroll C. Speir
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Patent number: 10340934Abstract: To address non-linearity, an on-chip linearization scheme is implemented along with an analog-to-digital converter (ADC) to measure and correct/tune for non-linearities and/or other non-idealities of the signal path having the ADC. The on-chip linearization scheme involves generating one or more test signals using an on-chip digital-to-analog converter (DAC) and providing the one or more test signals as input to the signal path to be linearized, and estimating non-linearity based on the one or more test signals and the output of the ADC. Test signals can include single-tone signals, multi-tone signals, and wideband signals spread over a range of frequencies. A time-delayed interleaving clocking scheme can be used to achieve a higher data rate for coefficient estimation without having to increase the sample rate of the ADC.Type: GrantFiled: December 18, 2017Date of Patent: July 2, 2019Assignee: ANALOG DEVICES, INC.Inventors: Nevena Rakuljic, Carroll C. Speir, Eric Otte, Corey Petersen, Jeffrey P. Bray
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Publication number: 20190190530Abstract: To address non-linearity, an on-chip linearization scheme is implemented along with an analog-to-digital converter (ADC) to measure and correct/tune for non-linearities and/or other non-idealities of the signal path having the ADC. The on-chip linearization scheme involves generating one or more test signals using an on-chip digital-to-analog converter (DAC) and providing the one or more test signals as input to the signal path to be linearized, and estimating non-linearity based on the one or more test signals and the output of the ADC. Test signals can include single-tone signals, multi-tone signals, and wideband signals spread over a range of frequencies. A time-delayed interleaving clocking scheme can be used to achieve a higher data rate for coefficient estimation without having to increase the sample rate of the ADC.Type: ApplicationFiled: December 18, 2017Publication date: June 20, 2019Applicant: Analog Devices, Inc.Inventors: Nevena RAKULJIC, Carroll C. SPEIR, Eric OTTE, Corey PETERSEN, Jeffrey P. BRAY
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Patent number: 10305495Abstract: Aspects of this disclosure relate to adjusting a phase of a clock signal provided to a device based on a feedback signal from the device. The feedback signal can provide phase information associated with the device and/or other information associated with the device, such as temperature information. A feedback signal processor can compute a phase control signal based on the feedback signal. The phase control signal can be used to adjust the phase of the clock signal. By adjusting the phase of one or more clock signals, several devices, such as data converters, can be synchronized.Type: GrantFiled: October 6, 2016Date of Patent: May 28, 2019Assignee: Analog Devices, Inc.Inventors: John Kevin Behel, Reuben Pascal Nelson, Matthew D. McShea, Matthew Louis Courcy, Kenny Gentile, Carroll C. Speir
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Publication number: 20180115406Abstract: A time-to-digital converter (TDC) detects a timing relationship between signals representing two temporal events. Several samples are acquired over a certain time period for each event, and the signals related to the different events are digitized or quantized either by separate TDCs or by a single TDC in a time-sequential manner. The quantized results are then processed, for example added to/ subtracted from one another, and used to determine the phase or time difference between the two events. When information being quantized is quasi-static over time periods where the measurement is performed, the instantaneous or “one shot” accuracy of a TDC need not be as good as or better than the desired time resolution. Digitally processing the signals and averaging the results moves an otherwise difficult analog quantizer problem to the digital domain where savings in power and chip area can be easily achieved without sacrificing accuracy.Type: ApplicationFiled: October 24, 2016Publication date: April 26, 2018Applicant: ANALOG DEVICES, INC.Inventors: RALPH D. MOORE, RYAN LEE BUNCH, CARROLL C. SPEIR
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Publication number: 20180102779Abstract: Aspects of this disclosure relate to adjusting a phase of a clock signal provided to a device based on a feedback signal from the device. The feedback signal can provide phase information associated with the device and/or other information associated with the device, such as temperature information. A feedback signal processor can compute a phase control signal based on the feedback signal. The phase control signal can be used to adjust the phase of the clock signal. By adjusting the phase of one or more clock signals, several devices, such as data converters, can be synchronized.Type: ApplicationFiled: October 6, 2016Publication date: April 12, 2018Inventors: John Kevin Behel, Reuben Pascal Nelson, Matthew D. McShea, Matthew Louis Courcy, Kenny Gentile, Carroll C. Speir
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Patent number: 9654133Abstract: Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.Type: GrantFiled: December 1, 2015Date of Patent: May 16, 2017Assignee: ANALOG DEVICES, INC.Inventors: Carroll C. Speir, Eric Otte, Nevena Rakuljic, Jeffrey Paul Bray
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Patent number: 9525428Abstract: Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.Type: GrantFiled: December 1, 2015Date of Patent: December 20, 2016Assignee: ANALOG DEVICES, INC.Inventors: Siddharth Devarajan, Eric Otte, Nevena Rakuljic, Carroll C. Speir
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Patent number: 9503116Abstract: Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.Type: GrantFiled: December 1, 2015Date of Patent: November 22, 2016Assignee: Analog Devices, Inc.Inventors: Carroll C. Speir, Eric Otte, Jeffrey Paul Bray
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Publication number: 20160182075Abstract: Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.Type: ApplicationFiled: December 1, 2015Publication date: June 23, 2016Applicant: ANALOG DEVICES, INC.Inventors: SIDDHARTH DEVARAJAN, ERIC OTTE, NEVENA RAKULJIC, CARROLL C. SPEIR
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Publication number: 20160182073Abstract: Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.Type: ApplicationFiled: December 1, 2015Publication date: June 23, 2016Applicant: ANALOG DEVICES, INC.Inventors: CARROLL C. SPEIR, ERIC OTTE, JEFFREY PAUL BRAY
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Publication number: 20160182074Abstract: Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.Type: ApplicationFiled: December 1, 2015Publication date: June 23, 2016Applicant: ANALOG DEVICES, INC.Inventors: CARROLL C. SPEIR, ERIC OTTE, NEVENA RAKULJIC, JEFFREY PAUL BRAY
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Patent number: 9184756Abstract: Embodiments of the present invention may provide a signal processing circuit that may comprises an analog-to-digital converter (ADC), and an output restriction circuit. The output restriction circuit may reduce the accuracy of the digital output of the ADC when signal content exceeds a pre-determined spectrum mask in an undesirable band. In one embodiment, the input signal spectrum may be actively monitored and when the input spectrum is inconsistent with an intended application, the output resolution may be restricted, for example, by truncating least significant bits (LSBs) of the digital output or adding digital noise.Type: GrantFiled: November 8, 2010Date of Patent: November 10, 2015Assignee: ANALOG DEVICES, INC.Inventors: Joseph Bradford Brannon, David Hall Robertson, James C. Camp, Carroll C. Speir
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Publication number: 20120114077Abstract: Embodiments of the present invention may provide a signal processing circuit that may comprises an analog-to-digital converter (ADC), and an output restriction circuit. The output restriction circuit may reduce the accuracy of the digital output of the ADC when signal content exceeds a pre-determined spectrum mask in an undesirable band. In one embodiment, the input signal spectrum may be actively monitored and when the input spectrum is inconsistent with an intended application, the output resolution may be restricted, for example, by truncating least significant bits (LSBs) of the digital output or adding digital noise.Type: ApplicationFiled: November 8, 2010Publication date: May 10, 2012Applicant: Analog Devices, Inc.Inventors: Joseph Bradford BRANNON, David Hall Robertson, James C. Camp, Carroll C. Speir