Abstract: A processor for calculating a convolution of a first input sequence of numbers with a second input sequence of numbers to generate an output sequence is provided. The processor includes multipliers, each multiplying two real numbers to generate an output; multiplexers to direct the numbers in the first and second input sequences or parts of the numbers to the multipliers; and control circuitry to control the multiplexers to direct the first and second input sequences of numbers to the multipliers dependent on whether the numbers are complex or real. An accumulator adds partial products from multiplications performed by the multipliers to calculate the convolution.

Abstract: A method includes receiving data in a first data processing module, and enabling a second data processing module when at least one signal time slot of the received data comprises data that complies with a first data transmission standard. The method also includes exchanging signals between the first data processing module and software executing in a processor, and determining that a software configuration of the second data processing module has been completed. The method also includes processing the data in the second data processing module for the at least one signal time slot, and enabling a third data processing module upon a completion of processing at least one data block in the second data processing module, and determining that a software configuration of the third data processing module has been completed, the at least one data block comprising multiple signal time slots.

Abstract: A channel impulse response (CIR)/DC offset (DCO) joint estimation for a time division synchronous code division multiple access (TDSCDMA) system includes generating from a basic midamble and received midamble an initial estimation of the CIR as a series of CIR taps; storing the initially estimated CIR taps; calculating a DC compensated CIR from the initially estimated CIR taps; filtering out the noise from the DC compensated CIR to produce the CIR estimation; and calculating the DC offset estimation from the CIR estimation.

Abstract: A wireless receiver uses a joint detection Viterbi (JDV) algorithm to demodulate a signal that has a desired signal component and an interference signal component. The desired signal component includes a training sequence and at least one data field. The training sequence and a corresponding portion of the interference signal component is demodulated using the JDV algorithm to evaluate possible transmitted training sequences and interference signal sequences, and channel estimations for the desired signal component and the interference signal component are generated. The at least one data field is demodulated according to the JDV algorithm using the channel estimations as initial channel estimates for the JDV algorithm.

Abstract: An apparatus for processing signals in a wireless system includes a first memory module to receive input data from a set of physical channels, a first plurality of sub-modules to process the input data. Each of the first plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a second memory module to receive processed input data and output intermediate data. Locations of the input data in the second memory is allocated in connection with data and transmission channel specifications. The apparatus also includes a second plurality of sub-modules to process the intermediate data. Each of the second plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a third memory module to receive and output bit rate processing output.

Abstract: A system includes a receiver for receiving a modulated signal. The receiver includes a gain estimator for converting complex data representative of constellation points of the modulated signal into scalar data representation. The gain estimator is configured to fold a first portion of the scalar data representation onto a second portion of the scalar data representation. The gain estimator is further configured to estimate a constellation gain value from the folded first portion and the second portion of the scalar data representation.

Abstract: A wireless receiver uses a joint detection Viterbi (JDV) algorithm to demodulate a signal that has a desired signal component and an interference signal component. The desired signal component includes a training sequence and at least one data field. The training sequence and a corresponding portion of the interference signal component is demodulated using the JDV algorithm to evaluate possible transmitted training sequences and interference signal sequences, and channel estimations for the desired signal component and the interference signal component are generated. The at least one data field is demodulated according to the JDV algorithm using the channel estimations as initial channel estimates for the JDV algorithm.

Abstract: A receiver adaptively selects between a joint detection Viterbi demodulator and a second Viterbi demodulator to demodulate a received signal based on at least one characteristic of the received signal. The joint detection Viterbi demodulator jointly demodulates a desired signal component and an interference signal component of the received signal, and the second Viterbi demodulator demodulates the desired signal component without demodulating the interference signal component.

Abstract: An apparatus for processing signals in a wireless system includes a first memory module to receive input data from a set of physical channels, a first plurality of sub-modules to process the input data. Each of the first plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a second memory module to receive processed input data and output intermediate data. Locations of the input data in the second memory is allocated in connection with data and transmission channel specifications. The apparatus also includes a second plurality of sub-modules to process the intermediate data. Each of the second plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a third memory module to receive and output bit rate processing output.

Abstract: A system includes a receiver for receiving a modulated signal. The receiver includes a gain estimator for converting complex data representative of constellation points of the modulated signal into scalar data representation. The gain estimator is configured to fold a first portion of the scalar data representation onto a second portion of the scalar data representation. The gain estimator is further configured to estimate a constellation gain value from the folded first portion and the second portion of the scalar data representation.

Abstract: A method includes receiving data in a first data processing module, and enabling a second data processing module when at least one signal time slot of the received data comprises data that complies with a first data transmission standard. The method also includes exchanging signals between the first data processing module and software executing in a processor, and determining that a software configuration of the second data processing module has been completed. The method also includes processing the data in the second data processing module for the at least one signal time slot, and enabling a third data processing module upon a completion of processing at least one data block in the second data processing module, and determining that a software configuration of the third data processing module has been completed, the at least one data block comprising multiple signal time slots.