Patents by Inventor Carsten Benthin

Carsten Benthin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260094231
    Abstract: An apparatus and method for efficiently managing ray tracing to reduce cache contention are contemplated. In various implementations, a computing system includes a host processing circuit sending commands of a video graphics application to a parallel data processing circuit. The cache memory subsystem of the parallel data processing circuit stores copies of data used for ray tracing operations. A cache access monitor tracks cache access metrics such as cache misses, cache evictions, and cache access latencies of the cache memory subsystem. A control circuit controls a number of rays that can be sent to the ray tracing circuit from compute circuits of the parallel data processing circuit. The control circuit uses the monitored cache access metrics to reduce or increase the number of rays being processed or serviced at any given time.
    Type: Application
    Filed: September 27, 2024
    Publication date: April 2, 2026
    Inventors: Carsten Benthin, Michael John Livesley
  • Publication number: 20260094343
    Abstract: Techniques herein involve building bounding volume hierarchies for ray tracing using neural networks. Bottom-up BVH building techniques include nearest neighbor search operations and tree construction operations. The nearest neighbor search operations evaluate a set of candidate nodes that do not have any parents to identify nearest neighbor pairs and the tree construction operations “combine” the nearest neighbor pairs by generating new nodes that are parents of the nodes of the pairs. The nearest neighbor search is an expensive operation as it generally considers all possible combinations of the set to select one considered “best.” A neural network model is thus proposed herein which can perform this nearest neighbor search in a more efficient manner. Specifically, the neural network model accepts, as input, information characterizing the nodes of a set for which a search is performed and provides, as output, information characterizing the nearest neighbor pairs found for the set.
    Type: Application
    Filed: September 27, 2024
    Publication date: April 2, 2026
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Carsten Benthin, Daniel Meister
  • Patent number: 12561753
    Abstract: Apparatus and method for prefetching node data. For example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to manage active ray tracing stack allocations within a traversal stack; and stack management hardware logic to issue a prefetch operation comprising an indication of bounding volume hierarchy (BVH) node data to be prefetched and an indication of a cache level, wherein responsive to performing the prefetch operation, the BVH node data is to be prefetched to the indicated cache level.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: February 24, 2026
    Assignee: Intel Corporation
    Inventors: Sven Woop, Carsten Benthin, Prasoonkumar Surti, Joshua Barczak, Abhishek R. Appu, Pawel Majewski
  • Patent number: 12548255
    Abstract: A method and apparatus for efficiently constructing a bounding volume hierarchy (BVH). For example, one embodiment of an apparatus comprises: a primitive sampler to identify a representative subset of input primitives of a graphics scene; bounding volume hierarchy (BVH) builder hardware logic to construct an approximate BVH based on the representative subset of input primitives; hardware logic to insert input primitives not in the representative subset into leaves of the approximate BVH; and the BVH builder or a different BVH builder to construct a final BVH based on the primitives inserted into the leaves of the approximate BVH.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: February 10, 2026
    Assignee: Intel Corporation
    Inventors: Lorenzo Tessari, Addis Dittebrandt, Michael Doyle, Carsten Benthin
  • Patent number: 12536732
    Abstract: Apparatus and method for efficient graphics processing including ray tracing. For example, one embodiment of a graphics processor comprises: execution hardware logic to execute graphics commands and render images; an interface to couple functional units of the execution hardware logic to a tiled resource; and a tiled resource manager to manage access by the functional units to the tiled resource, a functional unit of the execution hardware logic to generate a request with a hash identifier (ID) to request access to a portion of the tiled resource, wherein the tiled resource manager is to determine whether a portion of the tiled resource identified by the hash ID exists, and if not, to allocate a new portion of the tiled resource and associate the new portion with the hash ID.
    Type: Grant
    Filed: May 28, 2024
    Date of Patent: January 27, 2026
    Assignee: Intel Corporation
    Inventors: Sven Woop, Michael J. Doyle, Sreenivas Kothandaraman, Karthik Vaidyanathan, Abhishek R. Appu, Carsten Benthin, Prasoonkumar Surti, Holger Gruen, Stephen Junkins, Adam Lake, Bret G. Alfieri, Gabor Liktor, Joshua Barczak, Won-Jong Lee
  • Publication number: 20260011085
    Abstract: Apparatus and method for lossy displaced mesh compression. For example, one embodiment of an apparatus comprises: displacement mapping circuitry/logic to generate an original displacement-mapped mesh by performing a displacement mapping of a plurality of vertices of a base subdivision mesh; and mesh compression circuitry/logic to compress the original displacement-mapped mesh, the mesh compression circuitry/logic comprising a quantizer to quantize the displacement mapping of the plurality of vertices in view of a base mesh to generate a displacement array.
    Type: Application
    Filed: June 17, 2025
    Publication date: January 8, 2026
    Inventors: Sven WOOP, Karthik VAIDYANATHAN, Carsten BENTHIN
  • Publication number: 20260004506
    Abstract: A geometry compression format is described. The compression format eliminates the need to store duplicate vertex information by storing unique vertices in each compressed data structure. Different triangles can refer to the same vertex using an index value, which means that even if the same vertex is used multiple times in the compressed data structure, the entirety of the vertex information (e.g., positional information) does not need to be stored multiple times. While the format provides good compression characteristics, improvement can be gained by eliminating the indices and instead using an indication of an “implicit geometry.” The implicit geometry is a commonly-used geometry type that indicates a particular correspondence between unique vertices and triangles. In other words, by indicating an implicit geometry type, it is automatically known which vertices make up which triangles, and explicit index information does not need to be stored in the compressed data structure.
    Type: Application
    Filed: June 26, 2024
    Publication date: January 1, 2026
    Applicant: Advanced Micro Devices, Inc.
    Inventors: David Kirk McAllister, Carsten Benthin, Joshua David Barczak, Andrew Erin Kensler, Mohammed Ahmed Muneam Al-Obaidi
  • Publication number: 20260004507
    Abstract: A geometry compression format is described. The compression format eliminates the need to store duplicate vertex information by storing unique vertices in each compressed data structure. Different triangles can refer to the same vertex using an index value, meaning that even if the same vertex is used multiple times in the compressed data structure, the entirety of the vertex information (e.g., positional information) does not need to be stored multiple times. An improvement includes representing further subdivision of the geometry in an efficient manner to represent highly detailed geometry. The subdivision can be specified by sideband information which can specify any of a variety of types of information.
    Type: Application
    Filed: June 28, 2024
    Publication date: January 1, 2026
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Carsten Benthin, David Kirk McAllister, Joshua David Barczak
  • Publication number: 20250391058
    Abstract: A geometry compression format is described. The compression format eliminates the need to store duplicate vertex information by storing unique vertices in each compressed data structure. Different triangles can refer to the same vertex using an index value, meaning that even if the same vertex is used multiple times in the compressed data structure, the entirety of the vertex information (e.g., positional information) does not need to be stored multiple times. An improvement can be made to the dense geometry format to support interpolation. More specifically, in an example, geometry for two different interpolation points can be provided in a compressed data structure encoded using the dense geometry format. Using an interpolation parameter, new interpolated geometry can be derived from the two different interpolation points.
    Type: Application
    Filed: June 24, 2024
    Publication date: December 25, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Carsten Benthin, David Kirk McAllister, Joshua David Barczak
  • Publication number: 20250391095
    Abstract: Techniques herein propose utilization of the bounding volume hierarchy generated for ray tracing for the purposes of collision detection. In various examples, once an application has requested ray tracing operations be performed, thus resulting in building of a bounding volume hierarchy (“BVH”), the application also requests collision detection to be performed with that BVH. Such requests can be made to a driver, for example, which causes the collision detection tests to be performed using the previously generated BVH (for example, on the central processing unit (“CPU”) or on a graphics processing unit). This double use of the BVH provides efficiencies as compared with having completely separate rendering and collision detection operations.
    Type: Application
    Filed: June 21, 2024
    Publication date: December 25, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Carsten Benthin
  • Publication number: 20250391109
    Abstract: Techniques herein involve generating a bounding volume hierarchy in a fast and accurate manner. The techniques begin with a quickly built initial BVH and traverse that initial BVH in a bottom-up manner to generate a new BVH. The algorithm begins at the bottom level, setting the bottom-most primitive nodes as nodes in the new BVH and follows the initial BVH up, collecting uncombined nodes from lower levels to higher nodes. When the algorithm has collected a threshold number of such nodes at a node of the initial BVH, the algorithm builds a new subtree for that node by combining the threshold number of such nodes, and adds that new subtree to the new BVH. This algorithm is efficiently parallelizable by immediately switching from the traversal phase to the combining phase and using all work-items of a wavefront for such combining.
    Type: Application
    Filed: June 21, 2024
    Publication date: December 25, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Carsten Benthin
  • Patent number: 12499606
    Abstract: Apparatus and method for accelerating bounding box merge operations. For example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to be used to determine ray traversal results when traversing a ray through a bounding volume hierarchy (BVH), the BVH comprising a plurality of axis-aligned bounding boxes (AABBs); and a bounding box (BB) merge accelerator coupled to one or more execution units and coupled to a local memory in which to store a group of the AABBs, the BB merge accelerator, in response to the one or more EUs, to determine a second AABB to merge with a first AABB in accordance with a specified distance function.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: December 16, 2025
    Assignee: Intel Corporation
    Inventors: Carsten Benthin, Radoslaw Drabinski, Michael Doyle, Joshua Barczak
  • Patent number: 12487824
    Abstract: One embodiment provides a graphics processor including a processing resource including a register file, memory, a cache memory, and load/store/cache circuitry to process load, store, and prefetch messages from the processing resource. The circuitry includes support for an immediate address offset that will be used to adjust the address supplied for a memory access to be requested by the circuitry. Including support for the immediate address offset removes the need to execute additional instructions to adjust the address to be accessed prior to execution of the memory access instruction.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: December 2, 2025
    Assignee: Intel Corporation
    Inventors: Joydeep Ray, Abhishek R. Appu, Timothy R. Bauer, James Valerio, Weiyu Chen, Subramaniam Maiyuran, Prasoonkumar Surti, Karthik Vaidyanathan, Carsten Benthin, Sven Woop, Jiasheng Chen
  • Patent number: 12488530
    Abstract: Apparatus and method for camera-aware BVH re-braiding. For example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to be used to determine ray traversal results when traversing a ray through a bounding volume hierarchy (BVH); and BVH processing hardware logic to modify the BVH to reduce spatial overlap between one or more BVH subtrees based on a detected camera position to produce a modified BVH.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: December 2, 2025
    Assignee: Intel Corporation
    Inventors: Carsten Benthin, Radoslaw Drabinski, Joshua Barczak, Sven Woop, Holger H. Gruen, Pawel Majewski
  • Patent number: 12450833
    Abstract: Apparatus and method for box-box testing. For example, one embodiment of a processor comprises: a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged BVH nodes; traversal circuitry to traverse query boxes through the BVH, the traversal circuitry to read a BVH node from a top of a BVH node stack and to read a query box from a local storage or memory, the traversal circuitry further comprising: box-box testing circuitry and/or logic to compare maximum and minimum X, Y, and Z coordinates of the BVH node and the query box and to generate an overlap indication if overlap is detected for each of the X, Y, and Z dimensions; distance determination circuitry and/or logic to generate a distance value representing an extent of overlap between the BVH node and the query box; and sorting circuitry and/or logic to sort the BVH node within a set of one or more additional BVH nodes based on the distance value.
    Type: Grant
    Filed: February 26, 2024
    Date of Patent: October 21, 2025
    Assignee: Intel Corporation
    Inventors: Karthik Vaidyanathan, Carsten Benthin, Sven Woop
  • Publication number: 20250299417
    Abstract: A graphics processing apparatus comprising bounding volume hierarchy (BVH) construction circuitry to perform a spatial analysis and temporal analysis related to a plurality of input primitives and responsively generate a BVH comprising spatial, temporal, and spatial-temporal components that are hierarchically arranged, wherein the spatial components include a plurality of spatial nodes with children, the spatial nodes bounding the children using spatial bounds, and the temporal components comprise temporal nodes with children, the temporal nodes bounding their children using temporal bounds and the spatial-temporal components comprise spatial-temporal nodes with children, the spatial-temporal nodes bounding their children using spatial and temporal bounds; and ray traversal/intersection circuitry to traverse a ray or a set of rays through the BVH in accordance with the spatial and temporal components.
    Type: Application
    Filed: June 9, 2025
    Publication date: September 25, 2025
    Inventors: Sven WOOP, Attila AFRA, Carsten BENTHIN, Ingo WALD, Johannes GUENTHER
  • Publication number: 20250292487
    Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.
    Type: Application
    Filed: February 18, 2025
    Publication date: September 18, 2025
    Inventors: Karthik VAIDYANATHAN, Michael APODACA, Thomas RAOUX, Carsten BENTHIN, Kai XIAO, Carson BROWNLEE, Joshua BARCZAK
  • Patent number: 12361629
    Abstract: A graphics processing apparatus comprising bounding volume hierarchy (BVH) construction circuitry to perform a spatial analysis and temporal analysis related to a plurality of input primitives and responsively generate a BVH comprising spatial, temporal, and spatial-temporal components that are hierarchically arranged, wherein the spatial components include a plurality of spatial nodes with children, the spatial nodes bounding the children using spatial bounds, and the temporal components comprise temporal nodes with children, the temporal nodes bounding their children using temporal bounds and the spatial-temporal components comprise spatial-temporal nodes with children, the spatial-temporal nodes bounding their children using spatial and temporal bounds; and ray traversal/intersection circuitry to traverse a ray or a set of rays through the BVH in accordance with the spatial and temporal components.
    Type: Grant
    Filed: September 26, 2023
    Date of Patent: July 15, 2025
    Assignee: Intel Corporation
    Inventors: Sven Woop, Attila Afra, Carsten Benthin, Ingo Wald, Johannes Guenther
  • Patent number: 12340468
    Abstract: Apparatus and method for lossy displaced mesh compression. For example, one embodiment of an apparatus comprises: displacement mapping circuitry/logic to generate an original displacement-mapped mesh by performing a displacement mapping of a plurality of vertices of a base subdivision mesh; and mesh compression circuitry/logic to compress the original displacement-mapped mesh, the mesh compression circuitry/logic comprising a quantizer to quantize the displacement mapping of the plurality of vertices in view of a base mesh to generate a displacement array.
    Type: Grant
    Filed: March 15, 2020
    Date of Patent: June 24, 2025
    Assignee: Intel Corporation
    Inventors: Sven Woop, Karthik Vaidyanathan, Carsten Benthin
  • Publication number: 20250111609
    Abstract: Apparatus and method for converting lossy compressed geometry to bounding volume hierarchies. For example, one embodiment of a method comprises: constructing a bounding volume hierarchy (BVH) based on a compressed hierarchical LOD structure formed by iteratively merged pairs of clusters of geometric primitives, wherein constructing the BVH comprises: traversing the compressed hierarchical LOD structure to select a subset of clusters at one or more levels of the compressed hierarchical LOD structure based on a current view frustrum; decompressing each cluster and constructing a per-cluster BVH over the primitives of each cluster, each per-cluster BVH including a per-cluster BVH root node; and fusing the per-cluster BVH root nodes to form the BVH, the BVH to be used to efficiently ray trace all decompressed geometric primitives in the scene.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: CARSTEN BENTHIN, CHRISTOPH PETERS