Abstract: A power semiconductor module includes a power semiconductor die arranged on a power substrate, a housing enclosing the power semiconductor die and the power substrate, wherein an interior volume formed by the housing is divided by interior walls into at least a first compartment and a second compartment, wherein the power semiconductor die is arranged within the first compartment, a first encapsulation material encapsulating the power semiconductor die and at least partially filling the first compartment, and a second encapsulation material different from the first encapsulation material, the second encapsulation material encapsulating the first encapsulation material and at least partially filling the second compartment, wherein the first encapsulation material is arranged within the first compartment but not within the second compartment.

Abstract: A method includes: pouring a liquid, semi-liquid or viscous material into a cavity formed by sidewalls of a housing, to cover a substrate that is arranged in the cavity formed by the sidewalls; arranging a lid on the sidewalls, to cover the cavity formed by the sidewalls, the lid including at least one functional element that extends from the lid into the liquid, semi-liquid or viscous material in a direction towards the substrate once the lid is in a final mounting position; and curing the liquid, semi-liquid or viscous material, to form a casting compound.

Abstract: A method includes forming a first electrically conductive layer on a first side of a dielectric insulation layer, forming a structured mask layer on a side of the first electrically conductive layer that faces away from the dielectric insulation layer, forming at least one trench in the first electrically conductive layer, said at least one trench extending through the entire first electrically conductive layer to the dielectric insulation layer, forming a coating which covers at least the bottom and the side walls of the at least one trench, and removing the mask layer after the coating has been formed.

Abstract: A power semiconductor device includes a die carrier, a power semiconductor chip coupled to the die carrier by a first solder joint, a sleeve for a pin, the sleeve being coupled to the die carrier by a second solder joint, and a sealing mechanically attaching the sleeve to the die carrier, the sealing being arranged at a lower end of the sleeve, wherein the lower end faces the die carrier, and wherein the sealing does not cover the power semiconductor chip.

Abstract: A semiconductor die is disclosed. The semiconductor die includes a semiconductor body, a metallization over part of the semiconductor body and including a noble metal at a top surface of the metallization, a bondwire having a foot bonded to the top surface of the metallization, and a sealing material covering the foot of the bondwire, the top surface of the metallization, and one or more areas outside the top surface of the metallization where oxide and/or hydroxide-groups would be present if exposed to air. The sealing material adheres to the foot of the bondwire and the one or more areas outside the top surface of the metallization where the oxide and/or hydroxide-groups would be present if exposed to air.

Abstract: A method includes forming a first electrically conductive layer on a first side of a dielectric insulation layer, forming a structured mask layer on a side of the first electrically conductive layer that faces away from the dielectric insulation layer, forming at least one trench in the first electrically conductive layer, said at least one trench extending through the entire first electrically conductive layer to the dielectric insulation layer, forming a coating which covers at least the bottom and the side walls of the at least one trench, and removing the mask layer after the coating has been formed.

Abstract: A power semiconductor device includes a die carrier, a power semiconductor chip coupled to the die carrier by a first solder joint, a sleeve for a pin, the sleeve being coupled to the die carrier by a second solder joint, and a sealing mechanically attaching the sleeve to the die carrier, the sealing being arranged at a lower end of the sleeve, wherein the lower end faces the die carrier, and wherein the sealing does not cover the power semiconductor chip.

Abstract: A circuit carrier includes a dielectric isolation carrier, an upper metallization layer applied to the dielectric isolation carrier, and a dielectric coating. The upper metallization layer has a metallization section which has an underside facing the isolation carrier, a top side facing away from the isolation carrier, and a side surface closed in a ring-shaped fashion. The side surface laterally delimits the metallization section and extends continuously between the top side and the underside. The dielectric coating is on the side surface and the top side, and extends continuously from the side surface onto the top side.

Abstract: A circuit carrier includes a dielectric isolation carrier, an upper metallization layer applied to the dielectric isolation carrier, and a dielectric coating. The upper metallization layer has a metallization section which has an underside facing the isolation carrier, a top side facing away from the isolation carrier, and a side surface closed in a ring-shaped fashion. The side surface laterally delimits the metallization section and extends continuously between the top side and the underside. The dielectric coating is on the side surface and the top side, and extends continuously from the side surface onto the top side.

Abstract: A method of fabricating an integrated circuit comprising providing a substrate, forming a first layer on the substrate by electrochemical deposition using an electrolyte solution, and converting at least a portion of the first layer into a second layer by electrochemical oxidation using an electrolyte solution, the second layer being an oxide layer.