Abstract: Systems, methods, and circuitries are provided for generating an acceleration current in response to a threshold temperature being reached. In one example, temperature based acceleration current source circuitry includes a first temperature sensitive device, a second temperature sensitive device, differential trigger circuitry, and an acceleration current source. The first temperature sensitive device is configured to generate a first signal that varies responsive to temperature changes at a first rate. The second temperature sensitive device is configured to generate a second signal that varies responsive to temperature changes at a second rate. The differential trigger circuitry is configured to generate a trigger signal based on a difference between the first signal and the second signal. The acceleration current source circuitry is configured to output an acceleration current in response to the trigger signal.

Abstract: Systems, methods, and circuitries are provided for generating an acceleration current in response to a threshold temperature being reached. In one example, temperature based acceleration current source circuitry includes a first temperature sensitive device, a second temperature sensitive device, differential trigger circuitry, and an acceleration current source. The first temperature sensitive device is configured to generate a first signal that varies responsive to temperature changes at a first rate. The second temperature sensitive device is configured to generate a second signal that varies responsive to temperature changes at a second rate. The differential trigger circuitry is configured to generate a trigger signal based on a difference between the first signal and the second signal. The acceleration current source circuitry is configured to output an acceleration current in response to the trigger signal.

Abstract: An electronic device includes a digital-to-analog converter coupled to receive a reference voltage and a binary-encoded digital input signal. The electronic device provides an analog output signal that represents the value of the binary-encoded digital input signal and a transmission gate is coupled to pass the analog output signal. A blank pulse generator is coupled to receive selected bits of the binary-encoded digital input signal and to pulse the transmission gate off when the selected bits change value, thus providing a blanked analog output signal.

Abstract: A switching circuit includes back-to-back NMOS transistors coupled between first and second pins. A first PMOS transistor is coupled between an upper supply voltage and a first node and has a gate coupled to receive a first enable signal. First and second current mirrors are coupled in series to the first node and a resistor is coupled in parallel with the first current mirror. A first leg of the first and second current mirrors is coupled to a lower supply voltage through a second PMOS transistor and a second leg is coupled to the gates of the back-to-back NMOS transistors. The gate of the second PMOS transistor is coupled to a node that lies between the back-to-back NMOS transistors. Additional NMOS transistors couple the lower supply voltage to the gates and sources of the back-to-back NMOS transistors and also to the gate of the first current mirror.

Abstract: A circuit includes a digital-to-analog converter (DAC) having a DAC input and a DAC output. The circuit includes a reference voltage (VREF) generator having a VREF generator input, a VREF generator output, and a VREF power supply input. The VREF generator output is coupled to the DAC input. A voltage regulator has a voltage regulator input and a voltage regulator output. The voltage regulator output is coupled to the DAC. A clamp circuit has a first clamp circuit input, a second clamp circuit input, and a clamp circuit output. The first clamp circuit input is coupled to the voltage regulator input, and the clamp circuit output is coupled to the VREF power supply input. The second clamp circuit input is coupled to the voltage regulator output. The clamp circuit includes a source-follower circuit having the second clamp circuit input.

Abstract: A switching circuit includes back-to-back NMOS transistors coupled between first and second pins. A first PMOS transistor is coupled between an upper supply voltage and a first node and has a gate coupled to receive a first enable signal. First and second current mirrors are coupled in series to the first node and a resistor is coupled in parallel with the first current mirror. A first leg of the first and second current mirrors is coupled to a lower supply voltage through a second PMOS transistor and a second leg is coupled to the gates of the back-to-back NMOS transistors. The gate of the second PMOS transistor is coupled to a node that lies between the back-to-back NMOS transistors. Additional NMOS transistors couple the lower supply voltage to the gates and sources of the back-to-back NMOS transistors and also to the gate of the first current mirror.

Abstract: An electronic device includes a digital-to-analog converter coupled to receive a reference voltage and a binary-encoded digital input signal. The electronic device provides an analog output signal that represents the value of the binary-encoded digital input signal and a transmission gate is coupled to pass the analog output signal. A blank pulse generator is coupled to receive selected bits of the binary-encoded digital input signal and to pulse the transmission gate off when the selected bits change value, thus providing a blanked analog output signal.