Abstract: Access to a memory area by a first processor that executes a first processor program and a second processor that executes a second processor program is granted to one of the first processor and the second processor at a time. Access to the memory area by the first processor and the second processor are cyclically uniquely allocated (e.g., t?[(ad mod m)=o]) between the first and the second processor by the first and second processor programs.

Abstract: The invention relates to a FM simulcast broadcast signal, in which an analogue and digital signal are combined for a transmission in a transmission channel with limited bandwidth as a total signal (s), which has a first phase speed (vs), an auxiliary signal (hs) is prepared in the complex region from the modulated digital signal (ds) for transmission and the FM modulated analogue signal (as) for transmission, which has a second phase speed (vas). Said auxiliary signal (hs) is placed in a used or at least largely unused frequency range of the digital signal (ds). The total signal (s) for transmission comprises the auxiliary signal (hs) and the FM modulated digital signal (ds) and the first phase speed (vs) of the total signal (s) corresponds at least approximately to the second phase speed (vas) of the analogue signal (as).

Abstract: Access to a memory area by a first processor that executes a first processor program and a second processor that executes a second processor program is granted to one of the first processor and the second processor at a time. Access to the memory area by the first processor and the second processor are cyclically uniquely allocated (e.g., t?[(ad mod m)=o]) between the first and the second processor by the first and second processor programs.

Abstract: A processor architecture, for example, a SIMD processor architecture, includes at least two arithmetic/logic units to implement data processing, a data memory arrangement or a memory device interface to a memory arrangement to store data of different data types, an addressing unit to generate access addresses for the data to be stored in the data memory arrangement, and an address memory arrangement to store access addresses. The access addresses are logically linked to the given data type of the data, and/or a distribution of the data to the arithmetic/logic units is dependent on the access addresses, and/or a storage of the output data as the data is dependent on the access addresses.

Abstract: A cascaded integrator comb filter includes a first integrator that receives an input signal x[n] and provides an integrated signal, and a fractional integrator that also receives the input signal x[n] and provides a fractional integrated signal. A summer sums the integrated signal and the fractional integrated signal and provides a summed signal indicative thereof to a second integrator, which receives and integrates the summed signal to provide a second integrator output signal. A decimator unit receives the second integrator output signal and provides a decimated signal to a differentiator that receives the decimated signal and provides a differentiated signal.

Abstract: In a quadrature amplitude (QAM) demodulator, an auxiliary symbol may be utilized in place of the decision symbol to adjust the decision-feedback loops within the demodulator. For the formation and definition of the auxiliary symbol, the radius and angle information of the received signal or of the preliminary symbol may be used. Through use of the auxiliary symbol instead of the decision symbol, any error in the angle information due to the unknown frequency and phase deviation of the local oscillator may be ignored. An auxiliary symbol generator may be provided which, instead of assigning to the received signal an element from the predetermined symbol alphabet, generates an auxiliary symbol that lies on the most probable one of the nominal radii. Nominal radii may mean those radii on which in QAM the predetermined symbols of the alphabet lie in the plane determined by the quadrature signal pair. For the angle component of the auxiliary symbol, the angle information of the sampled digital signal may be used.

Abstract: The invention relates to a method and a circuit arrangement for determining the carrier frequency difference during the demodulating of received symbols (P1, P2) in the complex phase space (I, Q; R, ?) of a quadrature modulation method (QAM), wherein to determine the frequency the received symbols are compared with symbols (S1, S2) at nominal positions in the complex signal space. In order to make the determination independent of a rotation of the coordinate system of the received signals with respect to the coordinate system of the symbols, it is proposed to determine the angle (?(P1, P2)) between two received signal values (P1, P2) and compare it to possible nominal angles of the quadrature modulation method. An angle deviation between the determined angle of the received signal values and the nominal angle can be used as a direct measure of a frequency deviation (?f).

Abstract: Access to a memory area by a first processor that executes a first processor program and a second processor that executes a second processor program is granted to one of the first processor and the second processor at a time. Access to the memory area by the first processor and the second processor are cyclically uniquely allocated (e.g., t?[(ad mod m)=o]) between the first and the second processor by the first and second processor programs.

Abstract: The invention relates to a method for determining the sampling instant of a clock signal (ti) for a circuit for determining symbols (Se) from a digitized signal (sd, S) which is coupled to at least one quadrature signal pair of a modulation method (QAM), wherein the digitized signal is converted to polar signal coordinates (R, ?) with a radial component (R).

Abstract: The invention relates to a FM simulcast broadcast signal, in which an analogue and digital signal are combined for a transmission in a transmission channel with limited bandwidth as a total signal (s), which has a first phase speed (vs), an auxiliary signal (hs) is prepared in the complex region from the modulated digital signal (ds) for transmission and the FM modulated analogue signal (as) for transmission, which has a second phase speed (vas). Said auxlliary signal (hs) is placed in an used or at least largely unused frequency range of the digital signal (ds). The total signal (s) for transmission comprises the auxiliary signal (hs) and the FM modulated digital signal (ds) and the first phase speed (vs) of the total signal (s) corresponds at least approximately to the second phase speed (vas) of the analogue signal (as).

Abstract: A digital clock divider includes an adder and a clock division device configured to receive a first clock signal with a first frequency and to output a second clock signal having a lower frequency relative to the first frequency. The digital clock divider also includes a division value separation device and a feedback section. The division value separation device is configured to divide an addition value output from the adder into an integer value and a fractional value. The feedback section is configured to provide to the adder a feedback value, the feedback value comprising the fractional component or the fractional component modified by a processing device. The adder is configured to add the feedback value to an applied division value. The clock division device is controlled on the basis of the integer value.

Abstract: A cascaded integrator comb filter includes a first integrator that receives an input signal x[n] and provides an integrated signal, and a fractional integrator that also receives the input signal x[n] and provides a fractional integrated signal. A summer sums the integrated signal and the fractional integrated signal and provides a summed signal indicative thereof to a second integrator, which receives and integrates the summed signal to provide a second integrator output signal. A decimator unit receives the second integrator output signal and provides a decimated signal to a differentiator that receives the decimated signal and provides a differentiated signal.

Abstract: A system for decoding an electrical input signal includes a filter that impresses a variable gain on a portion of the input signal to deemphasize a spectral region of the input signal. The variable gain is set as a function of a variable gain control signal. A frequency detector generates the variable gain control signal in accordance with a frequency value wherein approximately one-half of the energy of the input signal is below the frequency value.

Abstract: The invention relates to a method for determining the sampling instant of a clock signal (ti) for a circuit for determining symbols (Se) from a digitized signal (sd, S) which is coupled to at least one quadrature signal pair of a modulation method (QAM), wherein the digitized signal is converted to polar signal coordinates (R, ?) with a radial component (R). In order to implement an optimization of the sampling instant independently of the frequency or phase offset of the carrier control on which the symbols depend, it is proposed that the rate-of-occurrence distribution of the signals over the radii, which are assigned to the modulation method within the complex plane, be considered at different sampling phases (?i, ?i2) as the quality value (G, G*), and that the better quality value be selected from among the multiple rate-of-occurrence determinations. The variation of the sampling phase assigned to this value is subsequently employed to correct the sampling clock signal (ti).

Abstract: Digital Clock Divider and Method for Operating a Digital Clock Divider A digital clock divider includes an adder and a clock division device configured to receive a first clock signal with a first frequency and to output a second clock signal having a lower frequency relative to the first frequency. The digital clock divider also includes a division value separation device and a feedback section. The division value separation device is configured to divide an addition value output from the adder into an integer value and a fractional value. The feedback section is configured to provide to the adder a feedback value, the feedback value comprising the fractional component or the fractional component modified by a processing device. The adder is configured to add the feedback value to an applied division value. The clock division device is controlled on the basis of the integer value.

Abstract: A linearization circuit with digital element matching for digital-to-analog converters includes an n-bit delta-sigma modulator that receives an input signal and provides a modulated n-bit signal. An encoder receives the modulated n-bit signal and provides an encoded signal (X) having 2n signal components (x0, x1, . . . , x2n?1). 2n digital-to-analog converter elements each receive an associated one of the 2n signal components (x0, x1, . . . , x2n?1) and provide an associated analog signal component (a0, a1, . . . , a2n?1) indicative thereof. A summer receives and sums the analog signal components to provide an analog output signal. A weighting factor supply device provides a first weighting factor (W+) for activated ones of the digital-to-analog converter elements and a second weighting factor (W?) for non-activated ones of the digital-to-analog converter elements, where the encoder is responsive to the first and second weighting factors.

Abstract: A technique of decoding a biphase signal comprises sampling the biphase signal to obtain phase sample values and sampling the biphase signal to obtain magnitude sample values. A first digital signal is derived from the phase sample values and associated bit combinations are formed from the first digital signal. A decision is made whether the bit combination is an erroneous bit combination, and a probability check is performed to obtain probability values that decide which parts of the erroneous bit combination are true and which are false. A corrected bit combination is generated from the obtained probability values, and a second digital signal is generated whose data states are formed from the valid bit combination and, in the presence of an erroneous bit combination, from the corrected bit combination.

Abstract: A storage device for a multibus architecture includes at least one memory to store data, information, and/or addresses, along with a memory connection having a port to connect the memory to one of the buses of the multibus architecture. The memory connection, the port, and the bus have data lines to transmit data along with address lines to transmit addresses, and/or control information to control the memory and other devices connected to each specific bus within the multibus architecture. A switching device selectively connects the memory connection to one of the buses to enable a memory access to transmit data, addresses, and/or control information to or from the selected one of these buses.

Abstract: Noise that is normally generated during the switching of a noise shaper may be reduced by switching the noise shaper to an inactive or off state after the occurrence of one or more predetermined criteria, for example the detection of a predetermined number of data values below a threshold value or equal to a certain value, or of a predetermined number of data values within a threshold region about a value that is constant with respect to the data values.

Abstract: A processor architecture, for example, a SIMD processor architecture, includes at least two arithmetic/logic units to implement data processing, a data memory arrangement or a memory device interface to a memory arrangement to store data of different data types, an addressing unit to generate access addresses for the data to be stored in the data memory arrangement, and an address memory arrangement to store access addresses. The access addresses are logically linked to the given data type of the data, and/or a distribution of the data to the arithmetic/logic units is dependent on the access addresses, and/or a storage of the output data as the data is dependent on the access addresses.