Abstract: The invention relates to a power amplifier having a phase amplification path with a phase amplification stage within said phase amplification path. Here the phase amplification stage receives a magnitude component of the power amplified output signal, and the phase amplification stage is responsive to a phase component of the input signal, a magnitude component of the input signal, and the received magnitude component of the power amplified output signal for generating the power amplified output signal. The invention also relates to a power amplifier having a magnitude amplification path for a magnitude component of the input signal with a magnitude amplifier stage within said magnitude amplification path, and with the power amplifier further having a phase amplification path with a phase amplification stage within said phase amplification path.

Abstract: The invention relates to a phase-locked loop comprising a voltage controlled oscillator and having a frequency control input for controlling the frequency of the output signal. The phase-locked loop also has a phase comparator for deriving a control signal from a phase error detected in response to a received output signal and a reference signal. The control signal is coupled to the frequency control input of said voltage controlled oscillator. The phase comparator includes a first and a second predefined phase step value to a first accumulated phase value, and the phase comparator has means for determining the phase error. The phase comparator may further have circuit means for performing a first and a second AND operation on the outputs from the first and second accumulators and for obtaining analogue signals corresponding to the outputs of the AND operations. The invention also relates to a method for obtaining information on a phase error between two signals.

Abstract: The invention relates to a power amplifier having a phase amplification path with a phase amplification stage within said phase amplification path. Here the phase amplification stage receives a magnitude component of the power amplified output signal, and the phase amplification stage is responsive to a phase component of the input signal, a magnitude component of the input signal, and the received magnitude component of the power amplified output signal for generating the power amplified output signal. The invention also relates to a power amplifier having a magnitude amplification path for a magnitude component of the input signal with a magnitude amplifier stage within said magnitude amplification path, and with the power amplifier further having a phase amplification path with a phase amplification stage within said phase amplification path.

Abstract: The invention relates to a phase-locked loop comprising a voltage controlled oscillator and having a frequency control input for controlling the frequency of the output signal. The phase-locked loop also has a phase comparator for deriving a control signal from a phase error detected in response to a received output signal and a reference signal. The control signal is coupled to the frequency control input of said voltage controlled oscillator. The phase comparator includes a first and a second predefined phase step value to a first accumulated phase value, and the phase comparator has means for determining the phase error. The phase comparator may further have circuit means for performing a first and a second AND operation on the outputs from the first and second accumulators and for obtaining analogue signals corresponding to the outputs of the AND operations. The invention also relates to a method for obtaining information on a phase error between two signals.

Abstract: Method for providing at least one inductance associated with a chip attached to a support, in which said inductances are provided by means of at least a first bondwire having first and second ends. In which method said first end of said first bondwire is bonded to a first pad on said chip by means of an automated process using the chip as a reference for placing the first end of the first bondwire on the first pad when bonding it thereto. The second end of said first bondwire is bonded to a second pad on said support by means of the automated process using the chip as a reference for placing the second end of the first bondwire on the second pad when bonding it thereto.

Abstract: Voltage controlled oscillator assembly which includes at least one voltage controlled oscillator, and a regulator for regulating the output power from the at least one voltage controlled oscillator.

Abstract: A current mirror circuit has an input portion including a first transistor, which is adapted to establish a reference current. It also has an output portion including a second transistor, and a control portion between the input portion and the output portion. The control portion includes a third transistor coupled for controlling the second transistor to generate an output current which is a function of the reference current while inhibiting current leakage from the input portion to the output portion. A lowpass filter is included in the control portion to prevent noise in the input portion from influencing the second transistor.

Abstract: A chip assembly comprising a chip mounted on a support is disclosed. The chip assembly comprises at least one terminal and discharge means for discharging a charge accumulated on or transferred to the at least one terminal. The discharge means is connected to an RF common mode node for at least one circuit on the chip.

Abstract: A current mirror circuit has an input portion including a first transistor, which is adapted to establish a reference current. It also has an output portion including a second transistor, and a control portion between the input portion and the output portion. The control portion includes a third transistor coupled for controlling the second transistor to generate an output current which is a function of the reference current while inhibiting current leakage from the input portion to the output portion. A lowpass filter is included in the control portion to prevent noise in the input portion from influencing the second transistor.

Abstract: Method for providing at least one inductance associated with a chip attached to a support, in which said inductances are provided by means of at least a first bondwire having first and second ends. In which method said first end of said first bondwire is bonded to a first pad on said chip by means of an automated process using the chip as a reference for placing the first end of the first bondwire on the first pad when bonding it thereto. The second end of said first bondwire is bonded to a second pad on said support by means of the automated process using the chip as a reference for placing the second end of the first bondwire on the second pad when bonding it thereto.

Abstract: Method for providing at least one inductance associated with a chip attached to a support, in which the inductances are provided by means of at least a first bondwire having first and second ends. In which method the first end of the first bondwire is bonded to a first pad on the chip by means of an automated process using the chip as a reference for placing the first end of the first bondwire on the first pad when bonding it thereto. The second end of the first bondwire is bonded to a second pad on the support by means of the automated process using the chip as a reference for placing the second end of the first bondwire on the second pad when bonding it thereto.

Abstract: Voltage controlled oscillator assembly, comprising at least one voltage controlled oscillator, and means for regulating the output power from the at least one voltage controlled oscillator.

Abstract: Voltage controlled oscillator assembly comprising means for detecting a control voltage input and means for generating an output frequency signal depending on said control voltage input. Said voltage controlled oscillator assembly comprises at least two voltage controlled oscillators, means for reading data from an external source, and means for individually switching the at least two voltage controlled oscillators on and off in accordance with the data read.

Abstract: Chip assembly comprising a chip mounted on a support, said chip assembly comprising at least one terminal and discharge means for discharging a charge accumulated on or transferred to said terminal. Said discharge means is connected to an RF common mode node for at least one circuit on the chip.