Abstract: A precision analog metal-metal capacitor is fabricated by forming a first capacitor plate in an insulation layer by forming a trench therein, depositing metal within the trench and planarizing the device. A thin dielectric layer is then deposited and patterned over the first capacitor plate. A second insulator is then deposited over the device and discrete openings etched therein to expose the insulation layer and first metal plate. Metal is deposited within the openings and planarized, thereby forming a contact to the first metal plate and the second metal plate of the capacitor.

Abstract: A method of forming sub-lithographic elements and spaces therebetween where the pitch may be reduced with continuously adjustable line and space dimensions, and a structure resulting from the method, are disclosed. A plurality of spaced convertible members are formed on a substrate. A portion of each member is then converted, thereby reducing the dimensions of the unconverted portion of the member while increasing the width of the member plus its converted layer. A conformal layer of material is then deposited over the converted members, followed by directional etching of the conformal layer. The unconverted portion of the member is then removed. The line and space dimensions can be continuously adjusted by altering either or both of the member's converted layer and conformal layer.

Abstract: A precision analog metal-metal capacitor is fabricated by forming a first capacitor plate in an insulation layer by forming a trench therein, depositing metal within the trench and planarizing the device. A thin dielectric layer is then deposited and patterned over the first capacitor plate. A second insulator is then deposited over the device and discrete openings etched therein to expose the insulation layer and first metal plate. Metal is deposited within the openings and planarized, thereby forming a contact to the first metal plate and the second metal plate of the capacitor.

Abstract: Fabrication methods and resultant semiconductor structures wherein stack structures are selectively insulated from an enveloping layer of local interconnect material. The fabrication methods involve forming an overpass insulator(s) simultaneously with the underlying gate. Specifically, a layer of non-erodible insulating material is deposited over a layer of conductive material roughly in the area to comprise the stack structure. A simultaneous etch is then performed, and the resultant insulator portion is self-aligned to the underlying conductive material. The insulator portion insulates the stack from a subsequently deposited and planarized layer of local interconnect. Further processing options include decoupling silicide formation on selected stack structures, and various planarization and etching approaches for different available technologies. Specific details of the fabrication methods and resultant structures are set forth.

Abstract: A semiconductor fabrication process for forming borderless contacts (130, 170, 172) using a removable mandrel (110). The process involves depositing a mandrel on an underlying barrier layer (100) designed to protect underlying structures (40) formed on a substrate (24). The mandrel is made from a material that will etch at a faster rate than the barrier layer so as to permit the formation of openings in the mandrel to be stopped on the barrier layer without penetrating such layer. After depositing a contact (130) in a first opening (120) formed in the mandrel, a second opening (140) is formed and a second contact (170) is deposited therein. Thereafter, the mandrel is removed and replaced with a layer of solid dielectric material (180).

Abstract: A gray level mask suitable for photolithography is constructed of a transparent glass substrate which supports plural levels of materials having different optical transmissivities. In the case of a mask employing only two of these levels, one level may be constructed of a glass made partially transmissive by substitution of silver ions in place of metal ions of alkali metal silicates employed in the construction of the glass. The second layer may be made opaque by construction of the layer of a metal such as chromium. The mask is fabricated with the aid of a photoresist structure which is etched in specific regions by photolithographic masking to enable selective etching of exposed regions of the level of materials of differing optical transmissivities. Various etches are employed for selective etching of the photoresist, the metal of one of the layers, and the glass of the other of the layers.

Abstract: Disclosed is a process for producing multi-level conductor/insulator films on a processed semiconductor substrate having a conductor pattern. The insulator layers, each comprise a photosensitive polyimide polymer composition, and this allows the desired wiring channels and stud vias to be formed directly in the insulator layers, without the use of separate masking layers and resulting image transfer steps, thus providing a less cumbersome and costly process.

Abstract: A gray level mask suitable for photolithography is constructed of a transparent glass substrate which supports plural levels of materials having different optical transmissivities. In the case of a mask employing only two of these levels, one level may be constructed of a glass made partially transmissive by substitution of silver ions in place of metal ions of alkali metal silicates employed in the construction of the glass. The second layer may be made opaque by construction of the layer of a metal such as chromium. The mask is fabricated with the aid of a photoresist structure which is etched in specific regions by photolithographic masking to enable selective etching of exposed regions of the level of materials of differing optical transmissivities. Various etches are employed for selective etching of the photoresist, the metal of one of the layers, and the glass of the other of the layers.

Abstract: A process is described which eliminates the need to account for mask alignment tolerances in forming vias for metallurgy by the use of a common vertical edge or common plane defined by a first mask representing a first level of interconnect. Subsequent masks for defining interconnecting vias and a second level of interconnect utilize at least one edge of the first mask pattern as a common element to define subsequent metal levels. The combination of an etch stop layer and an oversized second level mask enable the mask overlay to be eliminated.

Abstract: An improved VLSI or ULSI structure and a method of forming the same are provided. The structure starts with a base member having a plurality of supports formed thereon and extending upwardly therefrom. A selectively removable material is deposited on the base member and around the supports. An insulating cap is formed over the supports and the removable material. Access openings are provided through the cover (or base) and the removable material is removed through the access openings. Thereafter a partial vacuum is formed in the space evacuated by the removable material, and the access openings sealed to provide a dielectric medium around the supports and between the base and cap member having a dielectric constant of less than 2.0.

Abstract: A method for forming an electrically conductive line between two layers of insulating material and method for connecting the line through both layers of the insulating material to the opposite surfaces is provided. In the method, first, second and third layers of insulating material are provided wherein the first and third layers are separated by the second layer of insulating material which is different in etch rate from the first and third layers. The edge portion of all three layers is exposed and the insulating layer of the second material is selectively etched to remove the revealed edge portion and provide a slot between the first and third layers of insulating material. Also openings are provided in both the first and third layers of insulating material which communicate with the slot and extend respectively through the layers of the first and third insulating material.

Abstract: A sequence of masking steps reduces the amount of transference of a workpiece among work stations and reduces certain tolerances required for mask alignment in the construction of integrated circuits, and a gray level mask suitable for photolithography. In the integrated circuit, masking layers are developed directly in a wafer for delineating vertical and horizontal portions of an electrically conductive path. The mask is constructed of a transparent glass substrate which supports plural levels of materials having different optical transmissivities. In the case of a mask employing only two of these levels, one level may be constructed of a glass made partially transmissive by substitution of silver ions in place of metal ions of alkali metal silicates employed in the construction of the glass. The second layer may be made opaque by construction of the layer of a metal such as chromium.

Abstract: Disclosed is a process for producing multi-level conductor/insulator films on a processed semiconductor substrate having a conductor pattern. The insulator layers, each comprise a photosensitive polyimide polymer composition, and this allows the desired wiring channels and stud vias to be formed directly in the insulator layers, without the use of separate masking layers and resulting image transfer steps, thus providing a less cumbersome and costly process.

Abstract: Disclosed is an improved method of polishing a semiconductor wafer, which involves mounting the wafer to a wafer carrier comprising at least two materials having different coefficients of thermal expansion and regulating the temperature of the carrier, to thereby impart a convex (or concave) bias to the wafer. This provides an increased polishing action at the wafer center (or edges), so as to compensate for otherwise non-uniform radial polishing action across the wafer surface. Also disclosed, is an apparatus which incorporates the unique wafer carrier and temperature regulating means for achieving the desired degree of radial curvature of the wafer carrier.

Abstract: A method for forming reactive metal silicide layers at two spaced locations on a silicon substrate, which layers can be of different thicknesses and/or of different reactive metals is provided. A sililcon substrate has a silicon dioxide layer formed thereon followed by the formation of a polysilicon layer on the silicon dioxide layer, followed by forming a layer of refractory metal, e.g. titanium on the polysilicon. A non-reflecting material, e.g. titanium nitride is formed on the refractory metal. Conventional photoresist techniques are used to pattern the titanium nitride, the titanium and polysilicon, and the titanium is reacted with the contacted polysilicon to form a titanium silicide. The portion of silicon dioxide overlying the silicon substrate is then removed and the exposed substrate is ion implanted to form source/drain regions.

Abstract: A method for forming an electrically conductive line between two layers of insulating material and method for connecting the line through both layers of the insulating material to the opposite surfaces is provided. In the method, first, second and third layers of insulating material are provided wherein said first and third layers are separated by said second layer of insulating material which is different in etch rate from the first and third layers. The edge portion of all three layers is exposed and the insulating layer of the second material is selectively etched to remove the revealed edge portion and provide a slot between the first and third layers of insulating material. Also openings are provided in both the first and third layers of insulating material which communicate with the slot and extend respectively through the layers of the first and third insulating material.

Abstract: An improved VLSI and ULSI structure and a method of forming the same are provided. The structure starts with a base member having a plurality of supports formed thereon and extending upwardly therefrom. A selectively removable material is deposited on the base member and around the supports. An insulating cap is formed over the supports and the removable material. Access openings are provided through the cover (or base) and the removable material is removed through the access openings. Thereafter a partial vacuum is formed in the space evacuated by the removable material, and the access openings sealed to provide a dielectric medium around the supports and between the base and cap member having a dielectric constant of less than 2.0.

Abstract: A method of forming a plurality of conductive studs within a non-planar insulator layer (e.g., PSG or BPSG) disposed between a first series of conductive structures arranged on a substrate and metal lines formed on the upper surface of the insulator layer. Vertical vias are defined through the insulator layer to expose at least one of the first conductive structures on the substrate. A conformal metal layer (e.g., CVD W) is deposited on the insulator layer to fill the vias. Then, the metal layer and the insulator layer subjected to a polish etch in the presence of an abrasive slurry, to remove portions of the metal layer outside of the vias while simultaneously planarizing the insulator layer.

Abstract: A method of forming semi-conductor devices components wherein there are at least two exposed conducting regions having passivating material overlying said regions. The passivating material is subject to etching by a given etchant. At least one, but less than all of the regions are covered with a material, preferably an electrical conducting material, which also preferably covers additional electrical conducting or semi-conducting regions. Thereafter, all the regions are subjected to the given etchant, but only those regions having the passivating material not covered with the etch resistant material are removed. Preferably, at this point, a layer of conducting material is deposited over all the regions.

Abstract: A method for dry etching metals that form low volatility chlordes, in which Z-Cl reaction products are controllably introduced into a conventional Cl-based plasma independent of the workpiece. The Z-Cl products (e.g., AlCl.sub.3, GaCl.sub.3, etc.) are metal chlorides that have both electron acceptor and chloride donor properties. Thus, metals M (e.g., cobalt, copper and nickel) that usually produce low volatility chlorides can be controllably complexed to form high volatility Z.sub.x Cl.sub.y M.sub.z reaction products.