Patents by Inventor Carver A. Mead

Carver A. Mead has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5763909
    Abstract: A bipolar phototransistor comprises both an Integrating photosensor and a switching element. The base terminal of the bipolar phototransistor is utilized as the switch-control node for the pixel and its emitter is the output node of the integrating photosensor. A plurality of integrating photosensors may be placed in an array of rows and columns, wherein the bases of all bipolar phototransistors in a row are capacitively coupled together to a common row-select line, and the emitters of all bipolar phototransistors in a column are connected together to a column sense line. The input of a sense amplifier is connected to the sense line of each column of integrating photosensors. An integrating sense amplifier according to the present invention includes an amplifying element having an inverting input connected to the sense line. A capacitor, preferably a varactor, is also connected between the inverting input and output of the amplifying element.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: June 9, 1998
    Assignee: Synaptics, Incorporated
    Inventors: Carver A. Mead, Federico Faggin
  • Patent number: 5734191
    Abstract: A contactless capacitor coupled bipolar phototransistor having an integrated electronic shutter for reducing the overflow and blooming problems associated with the imaging of strong images. Overflow control and an anti-blooming mechanism are obtained by use of a second emitter (the "shutter") which is used to remove excess image generated charge. This prevents the base-emitter junction potential from becoming forward biased during image integration when the phototransistor is exposed to a strong image. The shutter is biased slightly lower than the first emitter of the phototransistor so that the base-shutter junction is forward biased sooner than the base-emitter junction when the imaging element is exposed to a strong image. The overflow current of the generated holes is then drained to the shutter, rather than into the emitter where it would produce noise on the column sense line.
    Type: Grant
    Filed: August 13, 1996
    Date of Patent: March 31, 1998
    Assignee: National Semiconductor Corporation
    Inventors: Min-Hwa Chi, Albert Bergemont, Carver Mead
  • Patent number: 5629891
    Abstract: A circuit for generating N analog voltage signals for reference or bias use employs N analog floating gate storage devices. Circuitry is provided so that all floating gate storage devices can be programmed to their target voltages individually or in parallel. Electron injection circuitry is provided for injecting electrons on to and a tunneling structure is provided for removing electrons from the floating gate of each floating gate storage device. A transistor structure with a lightly doped drain is provided for control of the tunneling structure. A capacitor is connected to each floating gate node to provide control of the injection structure. A dynamic analog storage element is provided to store the target voltage for the floating gate storage device. A comparator is provided to monitor the floating gate voltage and target voltage and control tunneling and injection. A digital storage device is provided to statically store the output of the comparator.
    Type: Grant
    Filed: March 25, 1996
    Date of Patent: May 13, 1997
    Assignee: Synaptics, Incorporated
    Inventors: John LeMoncheck, Timothy P. Allen, Gunter Steinbach, Carver A. Mead
  • Patent number: 5627392
    Abstract: A silicon MOS transistor with a time-varying transfer function is provided which may operate both as a single transistor analog learning device and as a single transistor non-volatile analog memory. The time-varying transfer function is achieved by adding or removing electrons from the fully insulated floating gate of an N-type MOS floating gate transistor. The transistor has a control gate capacitively coupled to the floating gate; it is from the perspective of this control gate that the transfer function of the transistor is modified. Electrons are removed from the floating gate via Fowler-Nordheim tunneling. Electrons are added to the floating gate via hot-electron injection.
    Type: Grant
    Filed: March 7, 1995
    Date of Patent: May 6, 1997
    Assignee: California Institute of Technology
    Inventors: Christopher J. Diorio, Paul E. Hasler, Bradley A. Minch, Carver A. Mead
  • Patent number: 5576237
    Abstract: A capacitor coupled contactless imager structure and a method of manufacturing the structure results in a phototransistor that structure includes an N-type collector region formed in P-type semiconductor material. A P-type base region is formed in the collector region. An n-doped polysilicon emitter contact is formed in contact with the surface of the P-type base region such that an n+ epitaxial region is formed in the base region as the emitter of the phototransistor. Silicon dioxide separates the poly1 emitter content and exposed surfaces at the base region from a layer of poly2 about 3000-4000 .ANG. thick that partially covers the base region; the gates of the CMOS peripheral devices are also poly2. The poly2 over the base region serves as a base coupling capacitor and a row conductor for the imager structure. The thickness of the poly2 capacitor plate allows it to be doped utilizing conventional techniques and silicided to improve the RC constant.
    Type: Grant
    Filed: October 17, 1995
    Date of Patent: November 19, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Albert Bergemont, Carver A. Mead, Min-hwa Chi, Hosam Haggag
  • Patent number: 5566044
    Abstract: A technique for decreasing the effective gain of a bipolar phototransistor at high light levels makes the image usable over a greatly extended range of illumination conditions. The effective current gain at high light levels is reduced by fabricating a "non-ideal" emitter, such as by inserting a thin 20 521 tunnel oxide between the emitter and base junction. The tunnel oxide between the emitter and base serves as a variable resistor as well as a good junction for carrier injection from the emitter. The total base voltage is the sum of the oxide voltage and the intrinsic base voltage. At high image intensity, the bipolar phototransistor will gradually enter into the saturation mode, i.e., the base to collector junction is forward biased. The beta is thus reduced. The bias of the collector should be about 0.3-0.8 V higher than the emitter at the 20.ANG. tunnel oxide thickness for optimum operation.
    Type: Grant
    Filed: May 10, 1995
    Date of Patent: October 15, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Albert Bergemont, Carver A. Mead, Min-hwa Chi, Hosam Haggag
  • Patent number: 5552619
    Abstract: A capacitor coupled contactless imager structure and a method of manufacturing the structure results is a phototransistor that structure includes an N-type collector region formed in P-type semiconductor material. A P-type base region is formed in the collector region. An n-doped polysilicon emitter contact is formed in contact with the surface to the P-type base region such that an n+ epitaxial region is formed in the base region as the emitter of the phototransistor. Silicon dioxide separates the poly1 emitter contact and exposed surfaces at the base region from a layer of poly2 about 3000-4000 .ANG. thick that partially covers the base region; the gates of the CMOS peripheral devices are also poly2. The poly2 over the base region serves as a base coupling capacitor and a row conductor for the imager structure. The thickness of the poly2 capacitor plate allows it to be doped utilizing conventional techniques and silicided to improve the RC constant.
    Type: Grant
    Filed: May 10, 1995
    Date of Patent: September 3, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Albert Bergemont, Carver A. Mead, Min-hwa Chi, Hosam Haggag
  • Patent number: 5541878
    Abstract: A circuit for generating N analog voltage signals for reference or bias use employs N analog floating gate storage devices. Circuitry is provided so that all floating gate storage devices can be programmed to their target voltages individually or in parallel. Electron injection circuitry is provided for injecting electrons on to and a tunneling structure is provided for removing electrons from the floating gate of each floating gate storage device. A transistor structure with a lightly doped drain is provided for control of the tunneling structure. A capacitor is connected to each floating gate node to provide control of the injection structure. A dynamic analog storage element is provided to store the target voltage for the floating gate storage device. A comparator is provided to monitor the floating gate voltage and target voltage and control tunneling and injection. A digital storage device is provided to statically store the output of the comparator.
    Type: Grant
    Filed: June 27, 1994
    Date of Patent: July 30, 1996
    Assignee: Synaptics, Incorporated
    Inventors: John LeMoncheck, Timothy P. Allen, Gunter Steinbach, Carver A. Mead
  • Patent number: 5488204
    Abstract: A proximity sensor system includes a touch-sensor pad with a sensor matrix array having a characteristic capacitance on horizontal and vertical conductors connected to sensor pads. The capacitance changes as a function of the proximity of an object or objects to the sensor matrix. The change in capacitance of each node in both the X and Y directions of the matrix due to the approach of an object is converted to a set of voltages in the X and Y directions. These voltages are processed by circuitry to develop electrical signals representative of the centroid of the profile of the object, i.e, its position in the X and Y dimensions. Noise reduction and background level setting techniques inherently available in the architecture are employed. A conductive paintbrush-type stylus is used to produce paint-like strokes on a display associated with the touch-sensor pad.
    Type: Grant
    Filed: October 17, 1994
    Date of Patent: January 30, 1996
    Assignee: Synaptics, Incorporated
    Inventors: Carver A. Mead, Ralph Wolf, Timothy P. Allen
  • Patent number: 5463348
    Abstract: A novel family of CMOS differential and transconductance amplifiers has wide input linear range and is suited for low power operation. The wide linear range is obtained by "widening the tanh", or decreasing the ratio of transconductance to bias current, by combining the three techniques of (a) using the well terminals of the input differential-pair transistors as the amplifier inputs; (b) using the feedback technique known as source degeneration; and (c) using the novel feedback technique of gate degeneration. According to one preferred embodiment of the present invention a compact transconductance amplifier having a linear range of .+-.1 V was achieved in an 11-transistor circuit with a DC-input operating range of 1 V-5 V in a low-power subthreshold CMOS technology in a standard 2 micron process.
    Type: Grant
    Filed: July 27, 1994
    Date of Patent: October 31, 1995
    Assignee: California Institute of Technology
    Inventors: Rahul Sarpeshkar, Carver A. Mead
  • Patent number: 5408194
    Abstract: A circuit for use as a channel of a minimum selector and subtractor circuit includes a P-Channel MOS transistor having a gate connected to an input node, a source connected to the output of a current source, and a drain connected to a fixed voltage source. The source of the P-Channel transistor is connectable to a common conductive line through a first switch. The source of the P-Channel transistor is also connected to the non-inverting input of a transconductance amplifier. The inverting input of the transconductance amplifier is connected to a first plate of a capacitor. The second plate of the capacitor is connected to a fixed voltage source such as ground. The output of the transconductance amplifier is connectable to its inverting input through a second switch. The output of the transconductance amplifier forms the output of the minimum selector and subtractor circuit. A plurality of individual channel circuits may all be connected to the common conductive line.
    Type: Grant
    Filed: June 25, 1993
    Date of Patent: April 18, 1995
    Assignee: Synaptics, Incorporated
    Inventors: Gunter Steinbach, Timothy P. Allen, Carver A. Mead
  • Patent number: 5376813
    Abstract: An adaptive photoreceptor semiconductor circuit for long-time-constant continuous learning having a low offset and insensitivity to light includes a photodiode in series with an MOS feedback transistor connected across a potential difference. An inverting amplifier comprises a first MOS amplifier transistor having its gate connected to a source of bias voltage potential in series with an cascode transistor having its gate connected to a source of cascode voltage potential and a second MOS amplifier transistor having its gate connected to the common connection between the photodiode and the MOS feedback transistor. An output node comprises the connection between the first MOS amplifier transistor and the cascode transistor. A light insensitive adaptive element has a driven node connected to the output node and an isolated node connected to the gate of the MOS feedback transistor. A capacitive voltage divider is connected between a first power supply rail, the adaptive element, and the output node.
    Type: Grant
    Filed: June 2, 1993
    Date of Patent: December 27, 1994
    Assignee: California Institute of Technology
    Inventors: Tobias Delbruck, Carver A. Mead
  • Patent number: 5331215
    Abstract: A synaptic array according to the present invention comprises a plurality of electrically-adaptable elements. Electrons may be placed onto and removed from a floating node in each electrically adaptable element associated with at least one MOS insulated gate field effect transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals generated in response to an adapt signal. The inputs to all synaptic elements in a row are connected to a common row input line. Adapt inputs to all synaptic elements in a column are connected together to a common column adapt line. The current supplied to all amplifiers in a column is commonly provided by a sense line.
    Type: Grant
    Filed: July 30, 1992
    Date of Patent: July 19, 1994
    Assignee: Synaptics, Incorporated
    Inventors: Timothy P. Allen, Janeen D. W. Anderson, Carver A. Mead, Federico Faggin, John C. Platt, Michael F. Wall
  • Patent number: 5324958
    Abstract: A bipolar phototransistor comprises both an integrating photosensor and a switching element. The base terminal of the bipolar phototransistor is utilized as the switch-control node for the pixel and its emitter is the output node of the integrating photosensor. A plurality of integrating photosensors may be placed in an array of rows and columns, wherein the bases of all bipolar phototransistors in a row are capacitively coupled together to a common row-select line, and the emitters of all bipolar phototransistors in a column are connected together to a column sense line. The input of a sense amplifier is connected to the sense line of each column of integrating photosensors. An integrating sense amplifier according to the present invention includes an amplifying element having an inverting input connected to the sense line. A capacitor, preferably a varactor, is also connected between the inverting input and output of the amplifying element.
    Type: Grant
    Filed: July 30, 1992
    Date of Patent: June 28, 1994
    Assignee: Synaptics, Incorporated
    Inventors: Carver A. Mead, Federico Faggin
  • Patent number: 5319268
    Abstract: A first and a second MOS transistor of the same conductivity type are connected in series between a load and a fixed voltage source. The gates of the first and second MOS transistors are connected to sources of input voltage which are of a magnitude smaller than the threshold voltages of the two MOS transistors. The first MOS transistor located next to the load is kept in saturation. A related circuit includes a first and a second MOS transistor of the same conductivity type are connected in series between a load and a fixed voltage source. The first MOS transistor located next to the load is kept in saturation. The gates of the first and second MOS transistors are connected to the gates of third and fourth diode-connected MOS transistors of the same conductivity type as the first and second MOS transistors. The third MOS transistor is connected between a first input current node and a fixed voltage source. The fourth MOS transistor is connected between a second input current node and a fixed voltage source.
    Type: Grant
    Filed: November 18, 1992
    Date of Patent: June 7, 1994
    Assignee: California Institute of Technology
    Inventors: Richard F. Lyon, Tobias Delbruck, Carver A. Mead
  • Patent number: 5303329
    Abstract: A continuous weight-update device for a synaptic element including at least one MOS transistor comprises a floating node having a capacitance associated therewith, the floating gate comprising at least a part of the floating node, first and second input lines, first and second error lines, an electron tunneling structure coupled to the floating node for tunneling electrons from the floating node, and an electron injecting structure coupled to the floating node for injecting electrons onto the floating node. Control circuitry is responsive to signals on the first input and error lines, for activating the electron tunneling structure, and control circuitry is responsive to signals on the second input and error lines, for activating the electron injecting structure. Circuitry is provided for driving signals onto the first and second input and error lines. Both a single synapse and an array of synapses incorporating the continuous weight-update device are also taught.
    Type: Grant
    Filed: December 10, 1991
    Date of Patent: April 12, 1994
    Assignee: Synaptics, Incorporated
    Inventors: Carver A. Mead, Janeen D. W. Anderson, John C. Platt
  • Patent number: 5289023
    Abstract: A photosensing pixel element comprises a bipolar phototransistor used as both an integrating photosensor and a select device. The phototransistor is a vertical structure, having as its collector a first doped region of a first conductivity type disposed in a semiconductor substrate or well structure. The base terminal of the bipolar phototransistor comprises a doped region of a second conductivity type disposed within the first doped region and is utilized as the select node for the pixel. Conventional field oxide regions may be employed to isolate the base regions of adjoining phototransistors. A polysilicon line doped to the first conductivity type is disposed over the surface of the semiconductor substrate and is insulated therefrom except in regions where it is in contact with the doped region of a second conductivity type to form an epitaxial emitter for the phototransistor. The polysilicon line also forms the emitter contact for the phototransistor.
    Type: Grant
    Filed: August 7, 1992
    Date of Patent: February 22, 1994
    Assignee: Synaptics, Incorporated
    Inventor: Carver A. Mead
  • Patent number: 5276407
    Abstract: A plurality of integrating photosensors is disposed in an array of rows and columns, with a given row select line connected to the gates of P-channel MOS transistors associated with that given row and a given column sense line connected to the drains of the P-channel MOS transistors associated with that given column. A sense amplifier is associated with each column. An integrating sense amplifier according to the present invention includes an amplifying element having an inverting input and a non-inverting input. The non-inverting input is connected to a source of reference voltage the inverting input is connected to a sense line. A P-channel balance transistor is connected between the inverting input and the output of the amplifying element and a capacitor is also connected between the inverting input and output of the amplifying element. A capacitor, preferably a varactor element, is connected between the output and the inverting input of the amplifying element.
    Type: Grant
    Filed: June 18, 1992
    Date of Patent: January 4, 1994
    Assignee: Synaptics, Incorporated
    Inventors: Carver A. Mead, Federico Faggin
  • Patent number: 5260592
    Abstract: A bipolar phototransistor comprises both an integrating photosensor and a switching element. The base terminal of the bipolar phototransistor is utilized as the switch-control node for the pixel and its emitter is the output node of the integrating photosensor. A plurality of integrating photosensors may be placed in an array of rows and columns, wherein the bases of all bipolar phototransistors in a row are capacitively coupled together to a common row-select line, and the emitters of all bipolar phototransistors in a column are connected together to a column sense line. The input of a sense amplifier is connected to the sense line of each column of integrating photosensors. An integrating sense amplifier according to the present invention includes an amplifying element having an inverting input connected to the sense line. A capacitor, preferably a varactor, is also connected between the inverting input and output of the amplifying element.
    Type: Grant
    Filed: September 16, 1991
    Date of Patent: November 9, 1993
    Assignee: Synaptics, Incorporated
    Inventors: Carver A. Mead, Federico Faggin
  • Patent number: 5243554
    Abstract: A circuit for generating N analog voltage signals for reference or bias use employs N analog floating gate storage devices. Electron injection circuitry is provided for injecting electrons on to and a tunneling structure is provided for removing electrons from the floating gate of each floating gate storage device. A follower amplifier is connected to each floating gate storage device and drives an analog output voltage bus. A capacitor is connected to each analog output storage bus. An analog pass gate is connected between each analog output voltage bus and a common monitor/dynamic load bus. Each analog pass gate is driven by a strobe signal.
    Type: Grant
    Filed: October 15, 1992
    Date of Patent: September 7, 1993
    Assignee: Synaptics, Incorporated
    Inventors: Timothy P. Allen, Adam K. Greenblatt, Carver A. Mead, Janeen D. W. Anderson