Abstract: A system and method for optimizing the object codes of a computer program is disclosed. The method includes receiving one or more object code units associated with an executable program; identifying, among the object code units, a first program entity and a first set of operations associated with the first program entity and a second program entity and a second set of operations associated with the second program entity, each program entity having an object code segment and an associated address; updating the object code units by inserting a predefined instruction before the first program entity's object code segment and causing the second set of operations to be associated with the predefined instruction if the first program entity's object code segment is identical to the second program entity's object code segment; and combining the updated object code units into the executable program.

Abstract: A system and method for optimizing the object code of a computer program is disclosed. The method includes receiving one or more object code units from the memory; identifying first and second identical program entities in the one or more object code units, wherein each program entity has an object code segment and an associated address; updating the one or more object code units by merging the first identical program entity with the second identical program entity if neither of the first and second program entities is subject to an operation on the respective program entity's address; and linking the updated one or more object code units into an executable program.

Abstract: A method for optimizing the object code of a program is disclosed. A compiler generates, respectively, first and second object code segments for first and second source code segments of the program. If the two object code segments are determined to be identical, the compiler generates first and second debugging information entries in a compilation unit of the program and both entries include information for locating the first object code segment. The compiler inserts two entries into a call table in the compilation unit, each entry including information for locating a respective call site that invokes a respective source code segment within a call stack of the program and information for locating a respective debug information entry. The call table is used for associating an operation within the first object code segment with one of the first and second source code segments at runtime.

Abstract: A method for debugging the object code of a program is disclosed. While executing an object code segment on an information processing device, a debugger receives a location identifier associated with the object code segment and identifies a call site within a call stack of the program using the location identifier. The call site is responsible for invoking the execution of the object code segment. Next, the debugger scans a call table for an entry of the call site that includes information for locating a debugging information entry within a compilation unit of the program. The debugger retrieves the debugging information entry from the compilation unit using the location information and identifies a unique one of multiple different source code segments as the one corresponding to the object code segment using a source code segment identifier in the debugging information entry.

Abstract: Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack including a plurality of register stack frames. Each of the register stack frames includes zero or more registers. One of the plurality of register stack frames is a current register stack frame. When execution of the instruction requires writing to a register referenced by the instruction, the instruction execution unit determines whether the register referenced by the instruction is within the current register stack frame. If the instruction execution unit determines that the register is not within the current register stack frame, the instruction execution unit does not execute the instruction and may, for example, generate a fault.

Abstract: Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack including a plurality of register stack frames. Each of the register stack frames includes zero or more registers. One of the plurality of register stack frames is a current register stack frame. When execution of the instruction requires writing to a register referenced by the instruction, the instruction execution unit determines whether the register referenced by the instruction is within the current register stack frame. If the instruction execution unit determines that the register is not within the current register stack frame, the instruction execution unit does not execute the instruction and may, for example, generate a fault.

Abstract: Method and apparatus for switching between multiple implementations of a routine. A plurality of implementations of a routine are compiled into respective object code modules. In one embodiment, each implementation of the routine is adapted for a particular hardware configuration. The different object code modules are associated with respective sets of hardware characteristics and with the name of the routine. When the application program and library are loaded into memory of the computer system, a references to the routine are resolved using the sets of hardware characteristics and the hardware configuration of the system.

Abstract: A method and system for enabling the registration of dynamically generated code and corresponding unwind information. In one embodiment, the present invention creates a module which includes data related to dynamically generated code and corresponding unwind information. The present embodiment also provides an application program interface which allows the data to be registered such that dynamic registration of the dynamically generated code and the corresponding unwind information is enabled.

Abstract: Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack including a plurality of register stack frames. Each of the register stack frames includes zero or more registers. One of the plurality of register stack frames is a current register stack frame. When execution of the instruction requires writing to a register referenced by the instruction, the instruction execution unit determines whether the register referenced by the instruction is within the current register stack frame. If the instruction execution unit determines that the register is not within the current register stack frame, the instruction execution unit does not execute the instruction and may, for example, generate a fault.

Abstract: Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack including a plurality of register stack frames. Each of the register stack frames includes zero or more registers. One of the plurality of register stack frames is a current register stack frame. When execution of the instruction requires writing to a register referenced by the instruction, the instruction execution unit determines whether the register referenced by the instruction is within the current register stack frame. If the instruction execution unit determines that the register is not within the current register stack frame, the instruction execution unit does not execute the instruction and may, for example, generate a fault.

Abstract: Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack including a plurality of register stack frames. Each of the register stack frames includes zero or more registers. One of the plurality of register stack frames is a current register stack frame. When execution of the instruction requires writing to a register referenced by the instruction, the instruction execution unit determines whether the register referenced by the instruction is within the current register stack frame. If the instruction execution unit determines that the register is not within the current register stack frame, the instruction execution unit does not execute the instruction and may, for example, generate a fault.

Abstract: A system and method are described for optimizing access of shared data. Briefly described, in architecture, the system can be implemented as follows. The data load optimization system includes a linkage table that contains at least one unresolved data module accessible by a computer program. The linkage table also includes a load determination logic that determines the location of the unresolved data module at load time of the computer program, and a load modification logic that modifies the load instruction in the computer program, at load time of the computer program, to directly load the unresolved data module at the location. The present invention can also be viewed as providing a method for efficiently accessing shared data.

Abstract: The present invention provides a system and method for providing a graphic representation of code characteristic and optimizations performed. In architecture, the system includes an optimizer display tool that indicates at least one instruction characteristic in a program and comprises logic that acquires a block of code in the program, and logic for analyzing the block of code for the at least one instruction characteristic. The optimizer display tool further comprises logic for generating a unique graphical indicator for the at least one instruction characteristic, and logic for displaying the unique graphical indicator with the block of code to indicate that the at least one instruction characteristic is present in the block of code.

Abstract: A method and system for enabling the registration of dynamically generated code and corresponding unwind information. In one embodiment, the present invention creates a module which includes data related to dynamically generated code and corresponding unwind information. The present embodiment also provides an application program interface which allows the data to be registered such that dynamic registration of the dynamically generated code and the corresponding unwind information is enabled.

Abstract: A system and method are described for optimizing access of shared data. Briefly described, in architecture, the system can be implemented as follows. The data load optimization system includes a linkage table that contains at least one unresolved data module accessible by a computer program. The linkage table also includes a load determination logic that determines the location of the unresolved data module at load time of the computer program, and a load modification logic that modifies the load instruction in the computer program, at load time of the computer program, to directly load the unresolved data module at the location. The present invention can also be viewed as providing a method for efficiently accessing shared data.

Abstract: A computer-implemented method and apparatus for transferring the contents of a general register, in a register stack, to a location in a backing store in a main memory are described. When transferring the contents of a general register to a location in the backing store, the invention proposes collecting attribute bits included in each general register of a predetermined group of registers in a temporary collection register. Once the temporary collection register has been filled, the contents of this register are written to the next available location in the backing store. Similarly, on the restoration of registers from the backing store, a collection of attribute bits saved in the backing register is transferred to a temporary collection register. Thereafter, each attribute bit is saved together with associated data into a general register, thereby to restore the former contents of each general register.

Abstract: A computer-implemented method of constructing a stack unwind data structure is described. In one embodiment, the method commences when a procedure, which comprises part of the computer program, is compiled. The stack unwind data structure construction commences with determining whether the called procedure complies with a default condition for a predetermined characteristic. For example, it may be determined whether a stack frame for the procedure is of a fixed or variable size, with a fixed size stack frame comprising a default condition. If the procedure does not comply with, or varies from, the default condition for this predetermined characteristic, then an unwind record for the procedure is generated, and included within an entry associated with the procedure in the stack unwind data structure. Alternatively, should the procedure comply with the default condition, this unwind record is not generated and accordingly not included within the stack unwind data structure.

Abstract: A computer-implemented method and apparatus for transferring the contents of a general register, in a register stack, to a location in a backing store in a main memory are described. When transferring the contents of a general register to a location in the backing store, the invention proposes collecting attribute bits included in each general register of a predetermined group of registers in a temporary collection register. Once the temporary collection register has been filled, the contents of this register are written to the next available location in the backing store. Similarly, on the restoration of registers from the backing store, a collection of attribute bits saved in the backing register is transferred to a temporary collection register. Thereafter, each attribute bit is saved together with associated data into a general register, thereby to restore the former contents of each general register.

Abstract: The inventive mechanism allows an application to switch modes during its operation, between a compatibility or legacy mode for a previous architecture, and a native mode for a current architecture. The mechanism includes an official function descriptor which describes information for accessing a function which resides in one module. The OFD has a legacy portion is useable by a legacy module and a native portion is useable by a native module. The mechanism also includes a linkage table that resides in a second module which references the function in the first module. The portion of the OFD which corresponds to the mode of the linkage table module is copied into the linkage table. Each portion contains one entry that corresponds to an address location of the function, and another entry that is a value for a register which refers to the data segment corresponding to the load module containing the function. The information in the OFD depends on whether the function is a legacy function or a native function.

Abstract: A computer-implemented method of switching contexts in a processor is provided. The processor includes a register stack (RS) that has first and second portions. The processor includes a register stack engine (RSE) to exchange information, in one of instruction execution dependent and independent modes between the second portion and the storage area. The computer implemented method of switching contexts includes the following steps: It is determined whether an interrupt occurred; a first register (IFM) configured to store a content of a second register (CFM) is invalidated, the CFM is configured to store control information related to the first portion; it is determined whether an interrupt handler needs to access the RS; and if so, the IFM is validated, the content of the CFM is copied to the IFM, and RSE is caused to exchange information between both the first and second portions of the RS and the storage area.