Abstract: System and method for configuring a system of heterogeneous hardware components, including at least one: programmable hardware element (PHE), digital signal processor (DSP) core, and programmable communication element (PCE). A program, e.g., a graphical program (GP), which includes floating point math functionality and which is targeted for distributed deployment on the system is created. Respective portions of the program for deployment to respective ones of the hardware components are automatically determined. Program code implementing communication functionality between the at least one PHE and the at least one DSP core and targeted for deployment to the at least one PCE is automatically generated. At least one hardware configuration program (HCP) is generated from the program and the code, including compiling the respective portions of the program and the program code for deployment to respective hardware components. The HCP is deployable to the system for concurrent execution of the program.

Abstract: Global optimization and verification of cyber-physical systems using graphical floating point math functionality on a heterogeneous hardware system (HHS). A program includes floating point implementations of a control program (CP), model of a physical system (MPS), objective function, requirements verification program (RVP), and/or global optimizer. A simulation simulates HHS implementation of the program using co-simulation with a trusted model, including simulating behavior and timing of distributed execution of the program on the HHS, and may verify the HHS implementation using the RVP. The HHS is configured to execute the CP and MPS concurrently in a distributed manner. After deploying the program to the HHS, the HHS is configured to globally optimize (improve) the CP and MPS executing concurrently on the HHS via the global optimizer. The optimized MPS may be usable to construct the physical system. The optimized CP may be executable on the HHS to control the physical system.

Abstract: Global optimization and verification of cyber-physical systems using graphical floating point math functionality on a heterogeneous hardware system (HHS). A program includes floating point implementations of a control program (CP), model of a physical system (MPS), objective function, requirements verification program (RVP), and/or global optimizer. A simulation simulates HHS implementation of the program using co-simulation with a trusted model, including simulating behavior and timing of distributed execution of the program on the HHS, and may verify the HHS implementation using the RVP. The HHS is configured to execute the CP and MPS concurrently in a distributed manner. After deploying the program to the HHS, the HHS is configured to globally optimize (improve) the CP and MPS executing concurrently on the HHS via the global optimizer. The optimized MPS may be usable to construct the physical system. The optimized CP may be executable on the HHS to control the physical system.

Abstract: System and method for configuring a system of heterogeneous hardware components, including at least one: programmable hardware element (PHE), digital signal processor (DSP) core, and programmable communication element (PCE). A program, e.g., a graphical program (GP), which includes floating point math functionality and which is targeted for distributed deployment on the system is created. Respective portions of the program for deployment to respective ones of the hardware components are automatically determined. Program code implementing communication functionality between the at least one PHE and the at least one DSP core and targeted for deployment to the at least one PCE is automatically generated. At least one hardware configuration program (HCP) is generated from the program and the code, including compiling the respective portions of the program and the program code for deployment to respective hardware components. The HCP is deployable to the system for concurrent execution of the program.

Abstract: System and method for configuring a system of heterogeneous hardware components, including at least one: programmable hardware element (PHE), digital signal processor (DSP) core, and programmable communication element (PCE). A program, e.g., a graphical program (GP), which includes floating point math functionality and which is targeted for distributed deployment on the system is created. Respective portions of the program for deployment to respective ones of the hardware components are automatically determined. Program code implementing communication functionality between the at least one PHE and the at least one DSP core and targeted for deployment to the at least one PCE is automatically generated. At least one hardware configuration program (HCP) is generated from the program and the code, including compiling the respective portions of the program and the program code for deployment to respective hardware components. The HCP is deployable to the system for concurrent execution of the program.

Abstract: System and method for configuring a system of heterogeneous hardware components, including at least one: programmable hardware element (PHE), digital signal processor (DSP) core, and programmable communication element (PCE). A program, e.g., a graphical program (GP), which includes floating point math functionality and which is targeted for distributed deployment on the system is created. Respective portions of the program for deployment to respective ones of the hardware components are automatically determined. Program code implementing communication functionality between the at least one PHE and the at least one DSP core and targeted for deployment to the at least one PCE is automatically generated. At least one hardware configuration program (HCP) is generated from the program and the code, including compiling the respective portions of the program and the program code for deployment to respective hardware components. The HCP is deployable to the system for concurrent execution of the program.

Abstract: System and method for configuring a system of heterogeneous hardware components, including at least one: programmable hardware element (PHE), digital signal processor (DSP) core, and programmable communication element (PCE). A program, e.g., a graphical program (GP), which includes floating point math functionality and which is targeted for distributed deployment on the system is created. Respective portions of the program for deployment to respective ones of the hardware components are automatically determined. Program code implementing communication functionality between the at least one PHE and the at least one DSP core and targeted for deployment to the at least one PCE is automatically generated. At least one hardware configuration program (HCP) is generated from the program and the code, including compiling the respective portions of the program and the program code for deployment to respective hardware components. The HCP is deployable to the system for concurrent execution of the program.

Abstract: System and method for debugging a graphical program deployed to hardware. The graphical program may be received. The graphical program may include a plurality of nodes and connections between the nodes which visually represents functionality of the graphical program. A hardware description may be generated based on the graphical program. The hardware description may describe a hardware implementation of the graphical program. The hardware description may be deployed to the programmable hardware element and the programmable hardware element may be executed. The graphical program may be displayed on a display of a host computer system that is coupled to the programmable hardware element. Debugging information may be received from the programmable hardware element during the executing. The debugging information from the programmable hardware element may be displayed in the graphical program displayed on the display.

Abstract: Generating a hardware description for a programmable hardware element based on a graphical program including multiple models of computation. A graphical program may be received which includes a first portion having a first computational model and a second portion having a second computational model. A hardware description may be generated based on the graphical program. The hardware description may describe a hardware implementation of the graphical program. The hardware description may be configured to configure a programmable hardware element to implement functionality of the graphical program.

Abstract: Generating a hardware description for a programmable hardware element based on a graphical program including multiple physical domains. A graphical program may be received which includes a first portion of a first physical domain for simulating a first portion of a physical system. The graphical program may include a second portion of a second physical domain for simulating a second portion of the physical system. A hardware description may be generated based on the graphical program. The hardware description may describe a hardware implementation of the graphical program. The hardware description may be configured to configure a programmable hardware element to simulate the physical system.

Abstract: Debugging a graphical program deployed on a programmable hardware element. The graphical program may be received. The graphical program may include a plurality of nodes and connections between the nodes which visually represents functionality of the graphical program. A hardware description may be generated based on the graphical program. The hardware description may describe a hardware implementation of the graphical program. The hardware description may be deployed to the programmable hardware element and the programmable hardware element may be executed. The graphical program may be displayed on a display of a host computer system that is coupled to the programmable hardware element. Debugging information may be received from the programmable hardware element during said executing. The debugging information from the programmable hardware element may be displayed in the graphical program displayed on the display.

Abstract: An arbitrary waveform generator including a digital signal procession unit and a memory. The digital signal processing unit may be configurable to interconnect a plurality of processing components in different configurations to process data received from the memory and perform one of a plurality of different functions to compute or enhance waveforms without having to store complex waveform data in the memory. In a first configuration, the digital signal processing unit may perform digital up-conversion functions on received waveform data to generate enhanced waveform data, and in a second configuration may perform data interpolation functions to generate enhanced waveform data. In a third configuration, the digital signal processing unit may receive data comprising attributes of a waveform from the memory and perform hardware-controlled arbitrary waveform generation functions.

Abstract: An instrumentation system may include a base card that is configurable to perform multiple instrumentation tasks. The base card includes a programmable logic device (PLD) that is configured according to a hardware description. One of a plurality of possible daughter cards, e.g., a first daughter card or a second daughter card, may be coupled to the base card. One or more of: 1) providing a selected hardware description to the PLD; or 2) coupling of a selected daughter card to the base card may configure the reconfigurable instrumentation card to perform a desired instrumentation function. Thus, by selecting which of the daughter cards is coupled to the base card and/or by selecting which hardware description is used to configure the PLD, the base card may be reconfigured to perform different sets of instrumentation tasks.

Abstract: A system and method for configuring a device to perform a function, where the device includes a programmable hardware element and one or more fixed hardware resources. A program is stored which represents the function. A hardware configuration program is generated based on the program, specifying a configuration for the programmable hardware element that implements the function, and usage of the fixed hardware resources by the programmable hardware element in performing the function. A deployment program deploys the hardware configuration program onto the programmable hardware element, where, after deployment, the device is operable to perform the function, where the programmable hardware element directly performs a first portion of the function, and the programmable hardware element invokes the fixed hardware resources to perform a second portion of the function. An optional measurement module couples to the device and performs signal conditioning and/or conversion logic on an acquired signal for the device.

Abstract: A system and method for debugging a program which is intended to execute on a reconfigurable device. A computer system stores a program that specifies a function, and which is convertible into a hardware configuration program (HCP) and deployable onto a programmable hardware element comprised on the device. The HCP is generated based on the program, specifies a configuration for the programmable hardware element that implements the function, and further specifies usage of one or more fixed hardware resources by the programmable hardware element in performing the function. A test configuration is deployable on the programmable hardware element by a deployment program, where, after deployment, the programmable hardware element provides for communication between the fixed hardware resources and the program. The program is executable by a processor in the computer system, where during execution the program communicates with the one or more fixed hardware resources through the programmable hardware element.

Abstract: A computer-implemented system and method for deploying a graphical program onto an image acquisition (IMAQ) device. The method may operate to configure an image acquisition (IMAQ) device to perform image processing or machine vision functions, wherein the device includes a programmable hardware element and/or a processor and memory. The method comprises first creating a graphical program which implements the image processing or machine vision function. A portion of the graphical program may be converted into a hardware implementation on a programmable hardware element, and a portion may optionally be compiled into machine code for execution by a CPU. The programmable hardware element is thus configured utilizing a hardware description and implements a hardware implementation of at least a portion of the graphical program. The CPU-executable code may be executed by a computer coupled to the IMAQ device, or by a processor/memory on the IMAQ device.

Abstract: A computer-implemented system and method for generating a hardware implementation of graphical code. The method may operate to configure an instrument to perform measurement functions, wherein the instrument includes a programmable hardware element. The method comprises first creating a graphical program, wherein the graphical program may implement a measurement function. A portion of the graphical program may be converted into a hardware implementation on a programmable hardware element, and a portion may optionally be compiled into machine code for execution by a CPU. The programmable hardware element is thus configured utilizing a hardware description and implements a hardware implementation of at least a portion of the graphical program.

Abstract: A video capture system and method whereby video frames or images, which are received in one of a plurality of possible formats, are acquired and stored into on-board memory in an image format. The image data can then be transferred into system memory at an optimum rate. The video capture system comprises a host computer, including a video capture board, which is coupled to a video source, such as a video camera. The video source provides digital video data in a first format of a plurality of different possible formats. The video capture board includes a memory controller which receives the digital video data in the first format and selectively provides the digital video data to the buffer memory in an image format. The memory controller includes address generation logic for generating buffer memory addresses for storing the video data to the buffer memory in the image format.

Abstract: An instrumentation system may include a base card that is configurable to perform multiple instrumentation tasks. The base card includes a programmable logic device (PLD) that is configured according to a hardware description. One of a plurality of possible daughter cards, e.g., a first daughter card or a second daughter card, may be coupled to the base card. One or more of: 1) providing a selected hardware description to the PLD; or 2) coupling of a selected daughter card to the base card may configure the reconfigurable instrumentation card to perform a desired instrumentation function. Thus, by selecting which of the daughter cards is coupled to the base card and/or by selecting which hardware description is used to configure the PLD, the base card may be reconfigured to perform different sets of instrumentation tasks.

Abstract: A computer-implemented system and method for generating a hardware implementation of graphical code. The method may operate to configure an instrument to perform measurement functions, wherein the instrument includes a programmable hardware element. The method comprises first creating a graphical program, wherein the graphical program may implement a measurement function. A portion of the graphical program may optionally be compiled into machine code for execution by a CPU, and another portion of the graphical program may be converted into a hardware implementation on a programmable hardware element. The programmable hardware element is configured utilizing a hardware description to produce a configured hardware element. The configured hardware element thus implements a hardware implementation of the second portion of the graphical program.