Patents by Inventor Casey King
Casey King has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967619Abstract: Laterally-gated transistors and lateral Schottky diodes are disclosed. The FET includes a substrate, source and drain electrodes, channel, a gate electrode structure, and a dielectric layer. The gate electrode structure includes an electrode in contact with the channel and a lateral field plate adjacent to the electrode. The dielectric layer is disposed between the lateral field plate and the channel. The lateral field plate contacts the dielectric layer and to modulate an electric field proximal to the gate electrode proximal to the drain or source electrodes. Also disclosed is a gate electrode structure with lateral field plates symmetrically disposed relative to the gate electrode. Also disclosed in a substrate with dielectric structures buried in the substrate remote from the gate electrode structure. A lateral Schottky diode having an anode structure includes an anode (A), cathodes (C) and lateral field plates located between the anode and the cathodes.Type: GrantFiled: September 16, 2020Date of Patent: April 23, 2024Assignee: TELEDYNE SCIENTIFIC & IMAGING, LLCInventors: Keisuke Shinohara, Casey King, Eric Regan, Miguel Urteaga
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Publication number: 20230411505Abstract: A FET with buried gate structures which contact an epitaxial channel layer only from the sides. The epitaxial channel layer preferably comprises multiple channel segments, the widths of which vary along the depth direction. By controlling the slope of the channel sidewalls and the distance between buried gate structures, the FET's transfer characteristics can be engineered to improve the FET's linearity.Type: ApplicationFiled: April 4, 2023Publication date: December 21, 2023Inventors: Keisuke Shinohara, Dean Regan, Casey King
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Patent number: 11605722Abstract: An ohmic contact for a multiple channel FET comprises a plurality of slit-shaped recesses in a wafer on which a multiple channel FET resides, with each recess having a depth at least equal to the depth of the lowermost channel layer. Ohmic metals in and on the sidewalls of each recess provide ohmic contact to each of the multiple channel layers. An ohmic metal-filled linear connecting recess contiguous with the outside edge of each recess may be provided, as well as an ohmic metal contact layer on the top surface of the wafer over and in contact with the ohmic metals in each of the recesses. The present ohmic contact typically serves as a source and/or drain contact for the multiple channel FET. Also described is the use of a regrown material to make ohmic contact with multiple channels, with the regrown material preferably having a corrugated structure.Type: GrantFiled: May 18, 2020Date of Patent: March 14, 2023Assignee: Teledyne Scientific & Imaging, LLCInventors: Keisuke Shinohara, Casey King, Eric Regan
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Patent number: 11477393Abstract: A method of view selection in a teleconferencing environment includes receiving a frame of image data from an optical sensor such as a camera, detecting one or more conference participants within the frame of image data, and identifying an interest region for each of the conference participants. Identifying the interest region comprises estimating head poses of participants to determine where a majority of the participants are looking and determining if there is an object in that area. If a suitable object is in the area at which the participants are looking, such as a whiteboard or another person, the image data corresponding to the object will be displayed on a display device or sent to a remote teleconference endpoint.Type: GrantFiled: March 17, 2021Date of Patent: October 18, 2022Assignee: PLANTRONICS, INC.Inventors: David A. Bryan, Wei-Cheng Su, Stephen Paul Schaefer, Alain Elon Nimri, Casey King
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Publication number: 20220085176Abstract: Laterally-gated transistors and lateral Schottky diodes are disclosed. The FET includes a substrate, source and drain electrodes, channel, a gate electrode structure, and a dielectric layer. The gate electrode structure includes an electrode in contact with the channel and a lateral field plate adjacent to the electrode. The dielectric layer is disposed between the lateral field plate and the channel. The lateral field plate contacts the dielectric layer and to modulate an electric field proximal to the gate electrode proximal to the drain or source electrodes. Also disclosed is a gate electrode structure with lateral field plates symmetrically disposed relative to the gate electrode. Also disclosed in a substrate with dielectric structures buried in the substrate remote from the gate electrode structure. A lateral Schottky diode having an anode structure includes an anode (A), cathodes (C) and lateral field plates located between the anode and the cathodes.Type: ApplicationFiled: September 16, 2020Publication date: March 17, 2022Inventors: Keisuke Shinohara, Casey King, Eric Regan, Miguel Urteaga
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Publication number: 20210359097Abstract: An ohmic contact for a multiple channel FET comprises a plurality of slit-shaped recesses in a wafer on which a multiple channel FET resides, with each recess having a depth at least equal to the depth of the lowermost channel layer. Ohmic metals in and on the sidewalls of each recess provide ohmic contact to each of the multiple channel layers. An ohmic metal-filled linear connecting recess contiguous with the outside edge of each recess may be provided, as well as an ohmic metal contact layer on the top surface of the wafer over and in contact with the ohmic metals in each of the recesses. The present ohmic contact typically serves as a source and/or drain contact for the multiple channel FET. Also described is the use of a regrown material to make ohmic contact with multiple channels, with the regrown material preferably having a corrugated structure.Type: ApplicationFiled: May 18, 2020Publication date: November 18, 2021Inventors: Keisuke Shinohara, Casey King, Eric Regan
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Publication number: 20210235024Abstract: A method of view selection in a teleconferencing environment includes receiving a frame of image data from an optical sensor such as a camera, detecting one or more conference participants within the frame of image data, and identifying an interest region for each of the conference participants. Identifying the interest region comprises estimating head poses of participants to determine where a majority of the participants are looking and determining if there is an object in that area. If a suitable object is in the area at which the participants are looking, such as a whiteboard or another person, the image data corresponding to the object will be displayed on a display device or sent to a remote teleconference endpoint.Type: ApplicationFiled: March 17, 2021Publication date: July 29, 2021Inventors: David A. BRYAN, Wei-Cheng SU, Stephen Paul SCHAEFER, Alain Elon NIMRI, Casey KING
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Patent number: 10999531Abstract: A method of view selection in a teleconferencing environment includes receiving a frame of image data from an optical sensor such as a camera, detecting one or more conference participants within the frame of image data, and identifying an interest region for each of the conference participants. Identifying the interest region comprises estimating head poses of participants to determine where a majority of the participants are looking and determining if there is an object in that area. If a suitable object is in the area at which the participants are looking, such as a whiteboard or another person, the image data corresponding to the object will be displayed on a display device or sent to a remote teleconference endpoint.Type: GrantFiled: January 27, 2020Date of Patent: May 4, 2021Assignee: Plantronics, Inc.Inventors: David A. Bryan, Wei-Cheng Su, Stephen Paul Schaefer, Alain Elon Nimri, Casey King
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Patent number: 10388746Abstract: A FET with a buried gate structure. The FET's gate electrode comprises a plurality of buried gate structures, the tops of which extend above the substrate's top surface and the bottoms of which are buried to a depth at least equal to that of the bottom of the channel layer, or the 2DEG plane within a channel layer for a HEMT, such that the buried gate structures contact the channel layer only from its sides. A head portion above and not in contact with the substrate's top surface contacts the tops of and interconnects all of the buried gate structures. Drain current is controlled by channel width modulation by lateral gating of the channel layer by the buried gates structures. The FET may include at least one field plate which comprises a slit structure in which the field plate is divided into segments.Type: GrantFiled: July 6, 2017Date of Patent: August 20, 2019Assignee: Teledyne Scientific & Imaging, LLCInventors: Keisuke Shinohara, Miguel Urteaga, Casey King, Andy Carter
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Patent number: 10249711Abstract: A FET employing a micro-scale device array structure comprises a substrate on which an epitaxial active channel area has been grown, with a plurality of micro-cells uniformly distributed over the active channel area. Each micro-cell comprises a source electrode, a drain electrode, and at least one gate electrode, with a first metal layer interconnecting either the drain or the source electrodes, a second metal layer interconnecting the gate electrodes, and a third metal layer interconnecting the other of the drain or source electrodes. Each micro-cell preferably comprises a source or drain electrode at the center of the micro-cell, with the corresponding drain or source electrode surrounding the center electrode. The number and width of the gate electrodes in each micro-cell may be selected to achieve a desired power density and/or heat distribution, and/or to minimize the FET's junction temperature. The FET structure may be used to form, for example, HEMTs or MESFETs.Type: GrantFiled: June 29, 2017Date of Patent: April 2, 2019Assignee: Teledyne Scientific & Imaging, LLCInventors: Keisuke Shinohara, Miguel Urteaga, Casey King, Avijit Bhunia, Ya-Chi Chen
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Publication number: 20190013386Abstract: A FET with a buried gate structure. The FET's gate electrode comprises a plurality of buried gate structures, the tops of which extend above the substrate's top surface and the bottoms of which are buried to a depth at least equal to that of the bottom of the channel layer, or the 2DEG plane within a channel layer for a HEMT, such that the buried gate structures contact the channel layer only from its sides. A head portion above and not in contact with the substrate's top surface contacts the tops of and interconnects all of the buried gate structures. Drain current is controlled by channel width modulation by lateral gating of the channel layer by the buried gates structures. The FET may include at least one field plate which comprises a slit structure in which the field plate is divided into segments.Type: ApplicationFiled: July 6, 2017Publication date: January 10, 2019Inventors: Keisuke Shinohara, Miguel Urteaga, Casey King, Andy Carter
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Publication number: 20190006464Abstract: A FET employing a micro-scale device array structure comprises a substrate on which an epitaxial active channel area has been grown, with a plurality of micro-cells uniformly distributed over the active channel area. Each micro-cell comprises a source electrode, a drain electrode, and at least one gate electrode, with a first metal layer interconnecting either the drain or the source electrodes, a second metal layer interconnecting the gate electrodes, and a third metal layer interconnecting the other of the drain or source electrodes. Each micro-cell preferably comprises a source or drain electrode at the center of the micro-cell, with the corresponding drain or source electrode surrounding the center electrode. The number and width of the gate electrodes in each micro-cell may be selected to achieve a desired power density and/or heat distribution, and/or to minimize the FET's junction temperature. The FET structure may be used to form, for example, HEMTs or MESFETs.Type: ApplicationFiled: June 29, 2017Publication date: January 3, 2019Inventors: Keisuke Shinohara, Miguel Urteaga, Casey King, Avijit Bhunia, Ya-Chi Chen
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Patent number: 8576924Abstract: A video processing apparatus and methodology are implemented as a combination of a processor and a video decoding hardware block to decode video data by performing piecewise processing of overlap smoothing and in-loop deblocking in a macroblock-based fashion. With this approach, a smaller on-board memory may be used for the in-loop filtering operations of the video decoding hardware block. By pipelining the piecewise processing operations, latency in the filtering operations is hidden and the filtering output is smoothed, thereby avoiding the need for bursts of fetching and storing of blocks.Type: GrantFiled: January 25, 2005Date of Patent: November 5, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Bill Kwan, Erik Schlanger, Casey King, Raquel Rozas
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Patent number: 7792385Abstract: A video processing apparatus and methodology are implemented as a combination of a processor and a video decoding hardware block to decode video data by providing the video decoding block with an in-loop filter and a scratch pad memory, so that the in-loop filter may efficiently perform piecewise processing of overlap smoothing and in-loop deblocking in a macroblock-based fashion which is a much more efficient algorithm than the frame-based method.Type: GrantFiled: January 25, 2005Date of Patent: September 7, 2010Assignee: GlobalFoundries Inc.Inventors: Bill Kwan, Erik Schlanger, Raquel Rozas, Casey King
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Publication number: 20060165164Abstract: A video processing apparatus and methodology are implemented as a combination of a processor and a video decoding hardware block to decode video data by providing the video decoding block with an in-loop filter and a scratch pad memory, so that the in-loop filter may efficiently perform piecewise processing of overlap smoothing and in-loop deblocking in a macroblock-based fashion which is a much more efficient algorithm than the frame-based method.Type: ApplicationFiled: January 25, 2005Publication date: July 27, 2006Applicant: Advanced Micro Devices, Inc.Inventors: Bill Kwan, Erik Schlanger, Raquel Rozas, Casey King
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Publication number: 20060165181Abstract: A video processing apparatus and methodology are implemented as a combination of a processor and a video decoding hardware block to decode video data by performing piecewise processing of overlap smoothing and in-loop deblocking in a macroblock-based fashion. With this approach, a smaller on-board memory may be used for the in-loop filtering operations of the video decoding hardware block. By pipelining the piecewise processing operations, latency in the filtering operations is hidden and the filtering output is smoothed, thereby avoiding the need for bursts of fetching and storing of blocks.Type: ApplicationFiled: January 25, 2005Publication date: July 27, 2006Applicant: Advanced Micro Devices, Inc.Inventors: Bill Kwan, Erik Schlanger, Casey King, Raquel Rozas