Abstract: By reconfiguring material in a recess formed in drain and source regions of SOI transistors, the depth of the recess may be increased down to the buried insulating layer prior to forming respective metal silicide regions, thereby reducing series resistance and enhancing the stress transfer when the corresponding transistor element is covered by a highly stressed dielectric material. The material redistribution may be accomplished on the basis of a high temperature hydrogen bake.

Abstract: By providing a protection layer on a silicon/germanium material of high germanium concentration, a corresponding loss of strained semiconductor material may be significantly reduced or even completely avoided. The protection layer may be formed prior to critical cleaning processes and may be maintained until the formation of metal silicide regions. Hence, high performance gain of P-type transistors may be accomplished without requiring massive overfill during the selective epitaxial growth process.

Abstract: By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.

Abstract: By forming thermocouples in a contact structure of a semiconductor device, respective extension lines of the thermocouples may be routed to any desired location within the die, without consuming valuable semiconductor area in the device layer. Thus, an appropriate network of measurement points of interest may be provided, while at the same time allowing the application of well-established process techniques and materials. Hence, temperature-dependent signals may be obtained from hot spots substantially without being affected by design constraints in the device layer.

Abstract: In sophisticated semiconductor devices, a strain-inducing semiconductor alloy may be positioned close to the channel region by forming cavities on the basis of a wet chemical etch process, which may have an anisotropic etch behavior with respect to different crystallographic orientations. In one embodiment, TMAH may be used which exhibits, in addition to the anisotropic etch behavior, a high etch selectivity with respect to silicon dioxide, thereby enabling extremely thin etch stop layers which additionally provide the possibility of further reducing the offset from the channel region while not unduly contributing to overall process variability.

Abstract: By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.

Abstract: In sophisticated semiconductor devices, a strain-inducing semiconductor alloy may be positioned close to the channel region by forming cavities on the basis of a wet chemical etch process, which may have an anisotropic etch behavior with respect to different crystallographic orientations. In one embodiment, TMAH may be used which exhibits, in addition to the anisotropic etch behavior, a high etch selectivity with respect to silicon dioxide, thereby enabling extremely thin etch stop layers which additionally provide the possibility of further reducing the offset from the channel region while not unduly contributing to overall process variability.

Abstract: By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.

Abstract: Operation of complex integrated circuits at low temperatures may be enhanced by providing active heating elements within the integrated circuit so as to raise the temperature of at least critical circuit portions at respective operational phases, such as upon power-up. Consequently, enhanced cold temperature performance may be obtained on the basis of existing process elements in order to provide design stability without requiring extensive circuit simulation or redesign of well-established circuit architectures.

Abstract: In sophisticated semiconductor devices, a strain-inducing semiconductor alloy may be positioned close to the channel region by forming cavities on the basis of a wet chemical etch process, which may have an anisotropic etch behavior with respect to different crystallographic orientations. In one embodiment, TMAH may be used which exhibits, in addition to the anisotropic etch behavior, a high etch selectivity with respect to silicon dioxide, thereby enabling extremely thin etch stop layers which additionally provide the possibility of further reducing the offset from the channel region while not unduly contributing to overall process variability.

Abstract: Transistor characteristics may be adjusted on the basis of asymmetrically formed cavities in the drain and source areas so as to maintain a strain-inducing mechanism while at the same time providing the possibility of obtaining asymmetric configuration of the drain and source areas while avoiding highly complex implantation processes. For this purpose, the removal rate during a corresponding cavity etch process may be asymmetrically modified on the basis of a tilted ion implantation process.

Abstract: By repeatedly applying a process sequence comprising an etch process and a selective epitaxial growth process during the formation of drain and source areas in a transistor device, highly complex dopant profiles may be generated on the basis of in situ doping. Further-more, a strain material may be provided while stress relaxation mechanisms may be reduced due to the absence of any implantation processes.

Abstract: By selectively applying a stress memorization technique to N-channel transistors, a significant improvement of transistor performance may be achieved. High selectivity in applying the stress memorization approach may be accomplished by substantially maintaining the crystalline state of the P-channel transistors while annealing the N-channel transistors in the presence of an appropriate material layer which may not to be patterned prior to the anneal process, thereby avoiding additional lithography and masking steps.

Abstract: By appropriately locally controlling the conditions during a re-growth process in a memory region and a speed-critical device region, the creation of dislocation defects may be reduced in the memory region, thereby enhancing overall stability of respective memory cells. On the other hand, enhanced strain levels may be obtained in the speed-critical device region by performing an efficient amorphization process and re-crystallizing amorphized portions, for instance, in the presence of a rigid material to provide a desired high strain level.

Abstract: By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.

Abstract: By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.

Abstract: By providing a high-k dielectric etch stop material as an etch stop layer for patterning an interlayer dielectric material, enhanced performance and higher flexibility may be achieved since, for instance, an increased amount of highly stressed dielectric material may be positioned more closely to the respective transistors due to the reduced thickness of the high-k dielectric etch stop material.

Abstract: In sophisticated semiconductor devices, a strain-inducing semiconductor alloy may be positioned close to the channel region by forming cavities on the basis of a wet chemical etch process, which may have an anisotropic etch behavior with respect to different crystallographic orientations. In one embodiment, TMAH may be used which exhibits, in addition to the anisotropic etch behavior, a high etch selectivity with respect to silicon dioxide, thereby enabling extremely thin etch stop layers which additionally provide the possibility of further reducing the offset from the channel region while not unduly contributing to overall process variability.

Abstract: Transistor characteristics may be adjusted on the basis of asymmetrically formed cavities in the drain and source areas so as to maintain a strain-inducing mechanism while at the same time providing the possibility of obtaining asymmetric configuration of the drain and source areas while avoiding highly complex implantation processes. For this purpose, the removal rate during a corresponding cavity etch process may be asymmetrically modified on the basis of a tilted ion implantation process.

Abstract: By repeatedly applying a process sequence comprising an etch process and a selective epitaxial growth process during the formation of drain and source areas in a transistor device, highly complex dopant profiles may be generated on the basis of in situ doping. Further-more, a strain material may be provided while stress relaxation mechanisms may be reduced due to the absence of any implantation processes.