Abstract: Data synchronization is achieved in devices which transmit and/or receive audio and/or video data through the staged locking of phase locked loops. According to an exemplary embodiment, a transmitter includes a serial data source. An encoder provides encoded data and includes a first PLL. A controller includes a second PLL which enables generation of a clock signal. The controller is coupled between the serial data source and the encoder for providing the clock signal to the encoder. The first PLL of the encoder locks to the clock signal.

Abstract: An apparatus includes a reception circuit with a frequency synthesizer, a decoder for digitally demodulating an audio file signal from the reception circuit, and a processor for initializing the decoder in response to a loss of a phase lock in the demodulating of the audio file signal and setting the frequency synthesizer at one of a plurality of frequencies to re-establish the phase lock in the demodulating of the audio file signal. The plurality of frequencies are 900 MHz range channel frequencies. Preferably, the plurality of frequencies are 905 MHz, 911 MHz, 917 MHz and 923 MHz. The decoder includes an eight-to-four modulation EFM digital decoder. Demodulating the audio file signal provides a digital audio stream conforming to an I2S audio format. The processor is preferably a microprocessor.

Abstract: An apparatus included a receiver for receiving an audio file signal, a decoder for demodulating the audio file signal; and a processor for polling the decoder for a loss of a phase lock in the demodulating of the audio file signal. The processor resets and reinitializes the decoder in response to the loss in the phase lock loop. The receiver includes 90 MHz radio frequency reception circuit. The decoder comprises an eight-to-four modulation EFM decoder. In the preferred embodiment, the decoder outputs a digital audio stream that conforms to a known I2S audio stream format.