Abstract: The invention relates to a method of generating and authenticating guaranteed unique identifier codes (CID) as may be used for identifying and authenticating assets comprising an integrated circuit, the method comprising; generating guaranteed unique identifiers (AID) in a centralized code registration system (3); storing the generated identifiers (AID) within a data storage (31a-31c); associating each identifier (AID) with an unique identification (CID) to be used for identifying an integrated circuit, by applying a bijective algorithm; authenticating an identification code (CID) by inversely calculating an identifier (AID) from an identification code (CID) based on said algorithm.

Abstract: For lithographically manufacturing a device with a very high density, a design mask pattern (120) is distributed on a number of sub-patterns (120a, 120b, 120c) by means of a new method. The sub-patterns do not comprise “forbidden” structures (135) and can be transferred by conventional apparatus to a substrate layer to be patterned. For the transfer, a new stack of layers is used, which comprise a pair of a processing layer (22; 26) and an inorganic anti-reflection layer (24; 28) for each sub-pattern. After a first processing layer (26) has been patterned with a first sub-pattern, it is coated with a new resist layer (30) which is exposed with a second sub-pattern, and a second processing layer (22) under the first processing layer is processed with the second sub-pattern.

Abstract: A sensor arrangement may be used to measure properties, such as optical properties, of a device arranged to process substrates. The sensor arrangement includes a substrate having the following: a plurality of sensor elements provided as an integrated circuit in the substrate, for each one of the plurality of sensor elements associated electronic circuitry comprising a processing circuit connected to the sensor element and an input/output interface connected to the processing circuit, and a power supply unit configured to supply operating power only to the electronic circuitry associated with one or more of the plurality of sensor elements which are in use. The at least one sensor element and possibly the processing electronics, the input/output unit, and/or the power supply unit may be provided as one or more integrated circuits or other structures in the substrate.

Abstract: For determining aberrations of an optical imaging system (PL), a test object (12,14) comprising at least one delta test feature (10) is imaged either on an aerial scanning detector (110) or in a resist layer (71), which layer is scanned by a scanning device, for example a SEM. A new analytical method is used to retrieve from the data stream generated by the aerial detector or the scanning device different Zernike coefficients (Zn).

Abstract: For lithographically manufacturing a device with a very high density, a design mask pattern (120) is distributed on a number of sub-patterns (120a, 120b, 120c) by means of a new method. The sub-patterns do not comprise “forbidden” structures (135) and can be transferred by conventional apparatus to a substrate layer to be patterned. For the transfer, a new stack of layers is used, which comprise a pair of a processing layer (22; 26) and an inorganic anti-reflection layer (24; 28) for each sub-pattern. After a first processing layer (26) has been patterned with a first sub-pattern, it is coated with a new resist layer (30) which is exposed with a second sub-pattern, and a second processing layer (22) under the first processing layer is processed with the second sub-pattern.

Abstract: The performance of a scanning electron microscope (SEM) (10) is determined by scanning, with this SEM, porous silicon surface areas (PSF, PSC) each having a different average pore size, calculating the Fourier transform spectra (Fc) of the images of the surface areas and extrapolating the resolution (R) at a zero signal-to-noise ratio (SNR) from the width (W(1/e)), the signal amplitude (Sa) and the noise offset (NL) of the spectra. A test sample provided with the different surface areas is obtained by anodizing a silicon substrate (Su) at a constant electric current, while continuously decreasing the substrate area exposed to the etching electrolyte (El).

Abstract: For lithographically manufacturing a device with a very high density, a design mask pattern (120) is distributed on a number of sub-patterns (120a, 120b, 120c) by means of a new method. The sub-patterns do not comprise “forbidden” structures (135) and can be transferred by conventional apparatus to a substrate layer to be patterned. For the transfer, a new stack of layers is used, which comprise a pair of a processing layer (22; 26) and an inorganic anti-reflection layer (24; 28) for each sub-pattern. After a first processing layer (26) has been patterned with a first sub-pattern, it is coated with a new resist layer (30) which is exposed with a second sub-pattern, and a second processing layer (22) under the first processing layer is processed with the second sub-pattern.

Abstract: A method is described for imaging, by means of projection radiation, a phase-shifting mask pattern on a substrate for the purpose of configuring device features in the substrate. By using a mask pattern comprising mask features constituted by a phase transition (22) and two sub-resolution assist features (40,41), arranged symmetrically with respect to the phase transition and having a mutual distance (p), device features having a wide variety of widths can be obtained by varying only the mutual distance.

Abstract: A method is described for imaging, by means of projection radiation, a phaseshifting mask pattern on a substrate for the purpose of configuring device features in the substrate. By using a mask pattern comprising mask features constituted by a phase transition (22) and two sub-resolution assist features (40,41), arranged symmetrically with respect to the phase transition and having a mutual distance (p), device features having a wide variety of widths can be obtained by varying only the mutual distance.