Patents by Inventor Casper A. Scalzi

Casper A. Scalzi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6681238
    Abstract: This invention describes a method and system for virtualizing an internal capability of a computing system; specifically, the invention describes a method and system for establishing a virtual machine containing a programmed hardware-machine function that is normally executed natively as proprietary internal code in its own hardware environment, a Central Electronics Complex (CEC) or logical partition of a CEC. The code resides in a separate hardware domain of the CEC called the Service Element (SE). The IBM VM/ESA (VM) operating system requests the SE to transfer a copy of the code into a virtual machine that VM has initialized, where the machine function is provided (in the current embodiment) as an isolated and encapsulated part of a virtual Parallel Sysplex system comprising multiple virtual CECs in a testing environment.
    Type: Grant
    Filed: March 24, 1998
    Date of Patent: January 20, 2004
    Assignee: International Business Machines Corporation
    Inventors: Frank W. Brice, Jr., Eugene P. Hefferon, Casper A. Scalzi, Richard P. Tarcza
  • Patent number: 6253224
    Abstract: This invention describes a method and system for virtualizing an internal capability of a computing system; specifically, the invention describes a method and system for establishing a virtual machine containing a programmed hardware-machine function that is normally executed natively as proprietary internal code in its own hardware environment, a Central Electronics Complex (CEC) or logical partition of a CEC. The code resides in a separate hardware domain of the CEC called the Service Element (SE). The IBM VM/ESA (VM) operating system requests the SE to transfer a copy of the code into a virtual machine that VM has initialized, where the machine function is provided (in the current embodiment) as an isolated and encapsulated part of a virtual Parallel Sysplex system comprising multiple virtual CECs in a testing environment.
    Type: Grant
    Filed: March 24, 1998
    Date of Patent: June 26, 2001
    Assignee: International Business Machines Corporation
    Inventors: Frank W. Brice, Jr., Eugene P. Hefferon, Casper A. Scalzi, Richard P. Tarcza
  • Patent number: 5987495
    Abstract: A method and apparatus for fully restoring the context of a user program, including program status word (PSW) and CPU register contents, following an asynchronous interrupt. Upon the occurrence of an asynchronous interrupt event, control is transferred from the normally executing part of the user program to an interrupt handler of the operating system kernel. The kernel interrupt handler saves the contents of the CPU registers and PSW as they existed at the time of the interrupt in a save area associated with the user program before transferring control to a signal catcher routine of the user program.
    Type: Grant
    Filed: November 7, 1997
    Date of Patent: November 16, 1999
    Assignee: International Business Machines Corporation
    Inventors: Donald F. Ault, Kenneth E. Plambeck, Casper A. Scalzi
  • Patent number: 5577231
    Abstract: A method of using the DAT mechanism in a computer processor to extend both: 1) the native storage access authorization architecture of the processor, and 2) to enable the processor to execute programs designed to operate under different storage access architectures. An executing program (called a source program) uses "source effective addresses" (source EAs) for locating its instructions and storage operands while executing on the processor (called the target processor).
    Type: Grant
    Filed: December 6, 1994
    Date of Patent: November 19, 1996
    Assignee: International Business Machines Corporation
    Inventors: Casper A. Scalzi, William J. Starke
  • Patent number: 5560013
    Abstract: A method of utilizing large virtual addressing in a target computer to implement an instruction set translator (1ST) for dynamically translating the machine language instructions of an alien source computer into a set of functionally equivalent target computer machine language instructions, providing in the target machine, an execution environment for source machine operating systems, application subsystems, and applications. The target system provides a unique pointer table in target virtual address space that connects each source program instruction in the multiple source virtual address spaces to a target instruction translation which emulates the function of that source instruction in the target system. The target system efficiently stores the translated executable source programs by actually storing only one copy of any source program, regardless of the number of source address spaces in which the source program exists.
    Type: Grant
    Filed: December 6, 1994
    Date of Patent: September 24, 1996
    Assignee: International Business Machines Corporation
    Inventors: Casper A. Scalzi, William J. Starke
  • Patent number: 5495614
    Abstract: A control process which enables a non-supervisory "using program" (e.g. application programs) to directly interface one or more shared asynchronous hardware facilities in a computer system. Any using program may request the operating system (OS) to set up a "special environment" with an AHF during which the using program can directly issue requests to the AHF for its services. The OS sets up a session for the using program having the "special environment", which specifies restrictions on storage accesses by the AHF for accesses made on behalf of the using program--to insure system data integrity. These restrictions are not changeable by the using program. The "special environment" exists until the session is ended by the using program or by a terminating condition.
    Type: Grant
    Filed: December 14, 1994
    Date of Patent: February 27, 1996
    Assignee: International Business Machines Corporation
    Inventors: Glen A. Brent, Thomas J. Dewkett, Casper A. Scalzi
  • Patent number: 5459864
    Abstract: Provides load balancing, recovery and reconfiguration control for a data move subsystem comprised of a plurality of interconnected and cooperating data move processors (DMPs). Each DMP processor has an associated queue for receiving queue elements (QEs) from central processing units of a data processing system which specify data move requirements of the data processing system. QEs can be transferred between queues of other DMPs or a common queue to achieve load balancing, recovery and reconfiguration control.
    Type: Grant
    Filed: February 2, 1993
    Date of Patent: October 17, 1995
    Assignee: International Business Machines Corporation
    Inventors: Glen A. Brent, Thomas J. Dewkett, Christine R. Panner, Casper A. Scalzi
  • Patent number: 5454086
    Abstract: Provides a dynamic execution link between an analyzer program and each hook instruction in a program. Special types of hook instructions are provided for use in a hooked program. The link causes the analyzer program to execute as part of a continuous uninterrupted execution for each hook instruction. The link uses hardware and/or internal code to access a hook control area which provides linkage information needed to invoke the execution of the analyzer program upon completion of the hook instruction and to continue the execution of the hooked program following the completion of the analyzer program. The linkage information includes the entry location into the analyzer program, and also locates the first hook work area (HWA) of a sequence of HWAs, from which an HWA is assigned to each current hook instruction. The assigned HWA stores a return point location in the hooked program at an instruction following the current hook instruction.
    Type: Grant
    Filed: August 11, 1992
    Date of Patent: September 26, 1995
    Assignee: International Business Machines Corporation
    Inventors: Alan I. Alpert, Carl E. Clark, Michel H. T. Hack, Casper A. Scalzi, Richard J. Schmalz, deceased, Bhaskar Sinha
  • Patent number: 5442802
    Abstract: Virtual addressing is available to a co-processor to asynchronously control the movement of multiple page units of data between different locations in the same or a different media, e.g. main store (MS) and expanded store (ES), or both may be in ES, or both may be in MS. The co-processor controls the asynchronous page movement in parallel with continuing execution of other instructions by the central processor (CP) which requested the page movement. Each page to be moved is specified by an MSB (Move Specification Block). A set of MSBs are addressed by a special type of channel control word (CCW) in a channel program containing one or more CCWs, some of which may address one or more sets of MSBs (one MSB set per CCW) to control the movement of any number of pages. The CPU executes a special ADM SSCH (start subchannel) instruction that passes the page move work to the co-processor to perform the requested page transfer involving one or more sets of MSBs.
    Type: Grant
    Filed: May 9, 1994
    Date of Patent: August 15, 1995
    Assignee: International Business Machines Corporation
    Inventors: Glen A. Brent, Thomas J. Dewkett, David B. Lindquist, Casper A. Scalzi
  • Patent number: 5426748
    Abstract: An addressing method using large addresses in a guest/host environment within a computer system. The guests are operating-systems, and the host is a hypervisor program. Each guest has a guest real address space (guest RAS) mapped onto a host large real address space (host LRAS) using means disclosed herein. To do this, each guest RAS is first assigned to a contiguous part of a host large virtual address space (LVAS) by assigning each guest RAS to one or more contiguous units of virtual addressing in the host LVAS, each unit having a 2 gigabyte (GB) size. The host LVAS is represented by a sequence of entries (ALEs) in a host access list (AL), in which each ALE represents a 2 GB unit of virtual addressing in the host LVAS. An ALE is selected in the AL by using a high-order part of a host large virtual address (host LVA) representing a guest RA or LRA. A host LVA is generated from a guest RA for obtaining the guest address in host main storage.
    Type: Grant
    Filed: January 3, 1992
    Date of Patent: June 20, 1995
    Assignee: International Business Machines Corporation
    Inventors: James G. Brenza, Joseph M. Gdaniec, Peter H. Gum, Kathryn M. Jackson, Mark M. Maccabee, Casper A. Scalzi, Bhaskar Sinha
  • Patent number: 5423013
    Abstract: Allows instructions and data to be located in any one or more of plural sections of a large-size real memory of a data processing system. Any memory section is located by concatenating a conventional small real/absolute address with an address extender used with conventional small-size memory. A Central Processor Extended Address Mode (CPEAM) register content indicates the location of extenders in an AR(s), ASTE(s), STE(s) or PTE(s) for use by a central processor or I/O operations. An Input-Output Extended Address Mode (IOEAM) register content indicates the location of the extenders in ORB(s), CCW(s) or IDAW(s) for use by I/O operations. A compatible mode sets the content to zero for either or both of the CPEAM and IOEAM if either or both is not to be used.
    Type: Grant
    Filed: September 4, 1991
    Date of Patent: June 6, 1995
    Assignee: International Business Machines Corporation
    Inventors: Richard I. Baum, Brent A. Carlson, Moon J. Kim, Michael G. Mall, Casper A. Scalzi, Bhaskar Sinha
  • Patent number: 5388244
    Abstract: Logical erasure is done for a virtual page unit of storage in a virtual-page-initialization process (even though the data content of a backing page frame is not physically erased). Pre-initialization controls are associated with each virtual page by a pre-initialization field in each page table entry (PTE). The pre-initialization controls operate differently for fetches and stores within the address translation process. Both fetches and stores test for a pre-initialization state in an F field in the PTE to control if and when any backing page frame can be accessed. While the F field bit is set to its pre-initialization state, no erasure writing is done in any backing page frame for a fetch or full-page store operation. An optional form identifier (form#) field is associated with the pre-initialization state field. The form# field content identifies one of plural form functions or form page frames.
    Type: Grant
    Filed: September 17, 1992
    Date of Patent: February 7, 1995
    Assignee: International Business Machines Corporation
    Inventors: Glen A. Brent, Casper A. Scalzi
  • Patent number: 5381537
    Abstract: A method and apparatus for translating a large logical address as a large virtual address (LVA) when a dynamic address translation (DAT) mode is on. Each LVA is separated into three concatenated parts: 1. a highest-order part (ADEN) for indexing into an access directory (AD) to locate an entry (ADE) for locating one access list (AL); 2. an intermediate part (ALEN) for indexing into a selected AL to access an entry (ALE) that enables location of an associated conventional address translation table which represents a conventional size virtual address space; and 3. a low-order DAT virtual address (VA) part having the same size as a conventional type of virtual address. The low-order DAT VA part is translated by the associated conventional address translation table. If a carry signal is generated during the creation of the low-order DAT VA part, then a change in the selection of an ALE results.
    Type: Grant
    Filed: December 6, 1991
    Date of Patent: January 10, 1995
    Assignee: International Business Machines Corporation
    Inventors: Richard I. Baum, Kenneth E. Plambeck, Casper A. Scalzi, Richard J. Schmalz, Bhaskar Sinha
  • Patent number: 5377337
    Abstract: Provides a software-to-software interface and a software-to-hardware interface between software users and a hardware ADM facility (ADMF) in a data processing system. Such software user presents only virtual addresses to the software-to-software interface in a MSB list. The user list defines virtual address spaces, including a "hiperspace", in a manner that represents physical backing media as different random-access electronic storages, such main storage (MS) and expanded storage (ES). The real data transfers are within or between the backing storages. The user list is transformed into an ADM operation block (AOB), which is assigned an ADM UCB in a UCB queue which is associated with an ADM subchannel. The software-to-hardware interface generates an ORB, containing the AOB address, as an operand of a SSCB instruction which is executed to queue the associated subchannel onto one of plural co-processor queues in the ADMF.
    Type: Grant
    Filed: June 8, 1993
    Date of Patent: December 27, 1994
    Assignee: International Business Machines Corporation
    Inventors: James Antognini, Glen A. Brent, Thomas E. Cook, Thomas J. Dewkett, Joseph C. Elliott, Francis E. Johnson, Casper A. Scalzi, Kenneth R. Veraska, Joseph A. Williams, Harry M. Yudenfriend
  • Patent number: 5361356
    Abstract: A Branch in Subspace Group (BSG) instruction is executed in problem state (for example by an application program) for providing a fast instruction branch between address spaces within a restricted group of address spaces called a subspace group. The subspace group contains two types of address spaces: a base space and any number of subspaces. The subspace group is set up in a control table associated with each dispatchable unit (DU). This DU control table contains: an identifier of a base space, an identifier of an access list that contains identifiers of all subspaces in the subspace group, an indicator of whether CPU control was last given to a subspace or to the base space, and an identifier of a last entered subspace in the group. The BSG instruction has an operand defining a general register containing the target virtual address and an associated access register containing an access-list-entry token (ALET) defining the target address space.
    Type: Grant
    Filed: March 6, 1992
    Date of Patent: November 1, 1994
    Assignee: International Business Machines Corporation
    Inventors: Carl E. Clark, Jeffrey A. Frey, Kenneth E. Plambeck, Casper A. Scalzi, Bhaskar Sinha
  • Patent number: 5237668
    Abstract: A single non-privileged instruction copies a page of data from a source virtual address in an electronic medium to a destination virtual address in the same or in a different electronic storage medium, and without the intervention of any supervisory program when each medium and the virtual addresses are previously determined. The instruction is not required to specify which medium it will use, does not require its user to know what backing medium it will access, does not require main storage (MS) to be its backing medium, and allows different types of physical addressing to be used by different media. The instruction can lock any page for use in a multi-processor (MP). No physical direction of data movement is provided within the non-privileged machine instruction, which only designates virtual direction of movement. The separation of virtual direction from physical direction is done by avoiding instruction control over selection of electronic media.
    Type: Grant
    Filed: October 20, 1989
    Date of Patent: August 17, 1993
    Assignee: International Business Machines Corporation
    Inventors: Geoffrey O. Blandy, David B. Emmes, Ronald F. Hill, David B. Lindquist, Kenneth E. Plambeck, Casper A. Scalzi, Richard J. Schmalz
  • Patent number: 5222215
    Abstract: A CPU interface recognizing a large very number of I/O interruption queues in a logically partitioned data processing system. Different partitions may contain different guest operating systems. The CPU interface controls how plural CPUs respond to I/O interruptions put on numerous hardware-controlled queues. A host hypervisor program dispatches the guest operating systems. The guests use the I/O interruptions in controlling the dispatching of their programs on the CPUs in a system. The invention allows the number of guest partitions in the system to exceed the number of I/O interruption subclasses (ISCs) architected in the system, and enables the dispatching controls of each guest operating system to be sensitive to different priorities for plural programs operating under a respective guest. The invention provides CPU controls that support alerting the host to enabled I/O interruptions, and provides CPU controlled pass-through for enabling direct guest handling of the guests I/O interruptions.
    Type: Grant
    Filed: August 29, 1991
    Date of Patent: June 22, 1993
    Assignee: International Business Machines Corporation
    Inventors: Norman C. Chou, Peter H. Gum, Roger E. Hough, Moon J. Kim, James C. Mazurowski, Donald W. McCauley, Casper A. Scalzi, John F. Scanlon, Leslie W. Wyman
  • Patent number: 5220669
    Abstract: A computer system has general purpose registers, control registers and access registers for containing information to allow address space capability. A linkage stack uses protected address space to store state information during program call and program return operations. The linkage stack contains information relating to state entries for the saved information and header and trailer entries to point to other linkage stack sections. A control register contains the pointer to the current linkage stack entry and is changed as the program call or return moves through the stack.
    Type: Grant
    Filed: July 19, 1991
    Date of Patent: June 15, 1993
    Assignee: International Business Machines Corporation
    Inventors: Richard I. Baum, Terry L. Borden, Carol E. Clark, Alan G. Ganek, James Lum, Michael G. Mall, Casper A. Scalzi, Richard J. Schmalz
  • Patent number: 5163096
    Abstract: Provides three access levels of storage key protection, comprising a supervisory level (key 0), an intermediate level of non-public and non-supervisory keys (keys 1-8, 10-15), and an unique public level (key 9). The program routines operating with a supervisory-level access key can access both the public level and the intermediate level of storage blocks. Although a program routine operating with an access key in the intermediary access level cannot access any supervisory level storage block, it can access any block assigned a public level storage key, as well as any storage block assigned the respective intermediate level key. One or more third-level public storage keys (PSKs) may be provided. A program access key using one of the PSK values can only access blocks having the same PSK value, and it cannot access blocks having any other key value.
    Type: Grant
    Filed: June 6, 1991
    Date of Patent: November 10, 1992
    Assignee: International Business Machines Corporation
    Inventors: Carl E. Clark, Michael G. Mall, Casper A. Scalzi, Bhaskar Sinha
  • Patent number: 5095420
    Abstract: A linear data set is mapped to one or more non-main storage virtual data spaces. Portions of this data space are then selectively mapped to a "window" in an address space in which an application is executing, and changes made in this "window" are temporarily saved in the data space. After completion of processing, the application may permanently save changed data from the data space to the linear data set.The technique for mapping the data space to the address space may be used to map between two address spaces, and may be extended to encompass third and subsequent spaces, so that a reference to a mapped address in the first space will ultimately be interpreted as a reference to an address in the last mapped space.
    Type: Grant
    Filed: November 21, 1988
    Date of Patent: March 10, 1992
    Assignee: International Business Machines
    Inventors: Catherine K. Eilert, Donald H. Gibson, Kenneth G. Rubsam, Casper A. Scalzi, Richard J. Schmalz, Eugene S. Schulze