Abstract: Six instructions for the manipulation of discontinuous memory locations in a computer memory are described. They are: Compare and Load (CL), Compare and Swap (CS), Double Compare and Swap (DCS), Compare and Swap and Store (CSST), Compare and Swap and Double Store (CSDST), and Compare and Swap and Triple Store (CSTST). In each instruction a processor associates a programming-specified blocking symbol with a lock not accessible to software. The lock is used by any of these instructions only during its single instance of instruction execution, and the lock is made available (unlocked) at the end of each instance to then enable another blocking-symbol instruction instance to use the lock, thereby serializing concurrent multiple processor requests for accessing the same resource. Programming associates resources in a system with the unique blocking symbols. Each instance of these instructions executes an operand earlier prepared from a data value taken from the resource..

Abstract: Preprocessing emulation methods utilizing search argument controls for a template routine address table in a target computing system. Target routines are stored in a target computing system for emulating incompatible instructions of an incompatible architecture which need not be recognized by the architecture of the target computing system. Preprocessing of template routines is preferrably executed on an Auxiliary Emulation Processor (AEP) which may access and patch (modify) some or all of the target instructions in any selected target routine and send them through a queue to a target processor for execution. Execution of the target routines on a target processor emulates the execution of incompatible instructions in an incompatible program in the incompatible architecture.

Abstract: Provides a program translation and execution method which stores target routines (for execution by a target processor) corresponding to incompatible instructions, interruptions and authorizations of an incompatible program written for execution on another computer system built to a computer architecture incompatible with the architecture of the target processor's computer system. The disclosed process allows the target processor to emulate incompatible acts expected in the operation of an incompatible program when the target processor itself is incapable of performing the emulated acts. Each of the instructions, interruptions and authorizations found in the incompatible programs has one or more corresponding target routines, any of which may need to be preprocessed before it can precisely emulate the execution results required by the incompatible architecture.

Abstract: Provides a processor method of executing instances of a Perform Locked Operation (PLO) instruction for enabling a recovery of the consistency of a resource unit being changed by a PLO instance when processor failure occurs anywhere during execution of the PLO instance. The method uses a PLO save area for each processor in a computer system capable of executing PLO instructions. Each PLO save area has a resource-inconsistency (RI) indicator having an RI state and a non-RI state, and stores the function code (FC) of the PLO instance. The RI state indicates that the resource is in a non-usable potentially inconsistent state, and the non-RI state indicates the resource is in the consistent state and may be used. A processor executing a PLO instance writes into its PLO save area all resource addresses where a change is to be made in the resource unit, and also writes in its PLO save area all operand values which will be used to change the resource at the associated addresses.

Abstract: Provides a processor CLE (CPU lock element) for each processor in a protected storage in a multi-processor computer system. Each CLE contains a blocking symbol field (called herein a PLT, program lock token, field), a lock field H, and a wait field W which is used to chain plural CLEs currently having the same blocking symbol. When the lock field H is set to a lock held state, it indicates the associated processor has exclusive rights to access a data resource unit associated with the blocking symbol in the CLE entry. When the wait field in a lock entry contains a pointer to another lock entry and the H field in the lock entry indicates a not held state, the associated processor is waiting for the resource and cannot further execute its PLO instance until it later gets set to the lock state, which is done by the processor of the prior CLE in the chain when it completes execution of its PLO instance. Each PLO instruction also has operand fields, and a function code (FC).

Abstract: PLO (perform locked operation) instructions containing blocking symbols are executed on each of multiple processors in a computer system to control coherence in data structures which may be changed by any of multiple processors in a computer system. The blocking symbol is extracted from a PLO instruction instance when invoked by its executing processor. Then the processor hashes the blocking symbol using hardware-microcode (H-M) to generate the location of a lock field in protected storage. The PLO instruction's blocking symbol is associated with a computer resource unit by software providing the PLO instruction, and the blocking symbol then associates the resource with a protected lock through the hashing operation on the blocking symbol. A processor must obtain the lock for a blocking symbol before the executing PLO instruction instance is allowed to make access and change the resource unit associated with the blocking symbol.

Abstract: A coexecutor for executing functions offloaded from central processors (CPs) in a data processing system, as requested by one or more executing control programs, which include a host operating system (host OS), and subsystem programs and applications executing under the host OS. The offloaded functions are embodied in code modules. Code modules execute in the coexecutor in parallel with non-offloaded functions being executed by the CPs. Thus, the CPs do not need to execute functions which can be executed by the coexecutor. CP requests to the coexecutor specify the code modules which are accessed by the coexecutor from host shared storage under the same constraints and access limitations as the control programs. The coexecutor may emulate host dynamic address translation, and may use a provided host storage key in accessing host storage. The restricted access operating state for the coexecutor maintains data integrity.