Abstract: A laser module includes one or more connectors and a laser source. The one or more connectors are configured to receive electrical power from, and to output a light beam to, a panel of a system. The laser source is configured to (i) be powered by the electrical power, and (ii) produce the light beam using the electrical power. The one or more connectors and the laser source are detachable from the panel, and when detached from the panel, the laser source is not powered by the electrical power.

Abstract: A laser module includes one or more connectors and a laser source. The one or more connectors are configured to receive electrical power from, and to output a light beam to, a panel of a system. The laser source is configured to (i) be powered by the electrical power, and (ii) produce the light beam using the electrical power. The one or more connectors and the laser source are detachable from the panel, and when detached from the panel, the laser source is not powered by the electrical power.

Abstract: A re-timer system that may include a phase recoverer (“PR”), first-in-first-out device (“FIFO”) and retime clock multiplication unit (“CMU”). PR may receive an input signal that suffers from jitter. PR may generate a phase matched signal having substantially the same phase as that of the input signal. To generate the phase matched signal, PR may use a clock signal provided by a single side band oscillator, CMU, or a clock signal having substantially the same level of jitter as that of the input signal to generate the phase matched signal. FIFO may sample the phase matched signal and store such samples. CMU may request and output samples from the FIFO at a frequency determined by a reference clock signal.

Abstract: A re-timer system that may include a phase recoverer (“PR”), first-in-first-out device (“FIFO”) and retime clock multiplication unit (“CMU”). PR may receive an input signal that suffers from jitter. PR may generate a phase matched signal having substantially the same phase as that of the input signal. To generate the phase matched signal, PR may use a clock signal provided by a single side band oscillator, CMU, or a clock signal having substantially the same level of jitter as that of the input signal to generate the phase matched signal. FIFO may sample the phase matched signal and store such samples. CMU may request and output samples from the FIFO at a frequency determined by a reference clock signal.

Abstract: A re-timer system that may include a phase recoverer (“PR”), first-in-first-out device (“FIFO”) and retime clock multiplication unit (“CMU”). PR may receive an input signal that suffers from jitter. PR may generate a phase matched signal having substantially the same phase as that of the input signal. To generate the phase matched signal, PR may use a clock signal provided by a single side band oscillator, CMU, or a clock signal having substantially the same level of jitter as that of the input signal to generate the phase matched signal. FIFO may sample the phase matched signal and store such samples. CMU may request and output samples from the FIFO at a frequency determined by a reference clock signal.

Abstract: A re-timer system that may include a phase recoverer (“PR”), first-in-first-out device (“FIFO”) and retime clock multiplication unit (“CMU”). PR may receive an input signal that suffers from jitter. PR may generate a phase matched signal having substantially the same phase as that of the input signal. To generate the phase matched signal, PR may use a clock signal provided by a single side band oscillator, CMU, or a clock signal having substantially the same level of jitter as that of the input signal to generate the phase matched signal. FIFO may sample the phase matched signal and store such samples. CMU may request and output samples from the FIFO at a frequency determined by a reference clock signal.

Abstract: A signal regenerator that reduces noise in a reference clock signal. In one possible implementation, phase comparisons between the reference clock signal and an input signal are made. Based on the phase comparisons, phases of a clock signal having a lower frequency than the reference clock signal are adjusted. Phases of the phase adjusted lower frequency clock signal are compared with phases of a divided down version of the reference clock signal. Based on such comparisons, phases of the reference clock signal may be adjusted.

Abstract: Techniques to determine and indicate the extent to which transitions of an input signal deviate from a desired transition region. In an implementation, an indication may be provided when a transition of an input signal occurs within the desired transition region and an indication may be provided when a transition of an input signal occurs outside the desired transition reagion. In an implementation, a difference between a number of times when input signal transitions occur inside and outside of the desired transition region may be provided. Accordingly, a receiver of the input signal may decide whether to ignore or use the input signal based on the difference between a number of times when input signal transitions occur inside and outside of the desired transition region.

Abstract: Techniques to adjust sampling times of an input signal. The techniques may utilize multi-level modification of the phase of a sampling clock. For example, the level of modification of the phase of the sampling clock may depend on the phase angle of the sampling clock in which transitions of the input signal occur.

Abstract: Briefly, a receiver system that may have an adjustable DC offset cancellation (vertical offset) and horizontal sampling point movement (horizontal offset) capabilities.

Abstract: A lock detection method for generating a lock signal including providing a data signal and a clock signal to a clock detection unit, the data signal being describable by an eye pattern, the data signal and the clock signal being in lock when a data transition occurs in the center of a first transition period.

Abstract: Techniques to adjust sampling times of an input signal.

Abstract: A signal regenerator that reduces noise in a reference clock signal.

Abstract: Techniques to determine and indicate the extent to which transitions of an input signal deviate from a desired transition region.

Abstract: A re-timer system that may include a phase recoverer (“PR”), first-in-first-out device (“FIFO”) and retime clock multiplication unit (“CMU”). PR may receive an input signal that suffers from jitter. PR may generate a phase matched signal having substantially the same phase as that of the input signal. To generate the phase matched signal, PR may use a clock signal provided by a single side band oscillator, CMU, or a clock signal having substantially the same level of jitter as that of the input signal to generate the phase matched signal. FIFO may sample the phase matched signal and store such samples. CMU may request and output samples from the FIFO at a frequency determined by a reference clock signal.

Abstract: A re-timer system that may include a phase recoverer (“PR”), first-in-first-out device (“FIFO”) and retime clock multiplication unit (“CMU”). PR may receive an input signal that suffers from jitter. PR may generate a phase matched signal having substantially the same phase as that of the input signal. To generate the phase matched signal, PR may use a clock signal provided by a single side band oscillator, CMU, or a clock signal having substantially the same level of jitter as that of the input signal to generate the phase matched signal. FIFO may sample the phase matched signal and store such samples. CMU may request and output samples from the FIFO at a frequency determined by a reference clock signal.