Abstract: Disclosed is an integrated circuit (IC) comprising a substrate (10) carrying a plurality of circuit elements; a metallization stack (12, 14, 16) interconnecting said circuit elements, said metallization stack comprising a patterned upper metallization layer comprising at least one sensor electrode portion (20) and a bond pad portion (22), at least the at least one sensor electrode portion of said patterned upper metallization layer being covered by a moisture barrier film (23); a passivation stack (24, 26, 28) covering the metallization stack, said passivation stack comprising a first trench (32) exposing the at least one sensor electrode portion and a second trench (34) exposing the bond pad portion; said first trench being filled with a sensor active material (36). A method of manufacturing such an IC is also disclosed.

Abstract: Disclosed is an integrated circuit comprising a substrate (10) carrying plurality of circuit elements (20); a metallization stack (30) over said substrate for providing interconnections to at least some of said circuit elements, the metallization stack comprising a plurality of patterned metal layers (31) spatially separated from each other by respective electrically insulating layers (32), at least some of said electrically insulating layers comprising conductive portions (33) that electrically interconnect portions of adjacent metal layers, wherein at least one of the patterned metallization layers comprises a plurality of ion-sensitive electrodes (34), each ion-sensitive electrode being electrically connected to at least one of said circuit elements, a plurality of sample volumes (50) extending into said metallization stack, each sample volume terminating at one of said ion-sensitive electrodes; and an ion-sensitive layer lining at least the ion-sensitive electrodes in said sample volumes.

Abstract: Disclosed is an integrated circuit comprising a substrate (10) carrying plurality of circuit elements (20); a metallization stack (30) over said substrate for providing interconnections to at least some of said circuit elements, the metallization stack comprising a plurality of patterned metal layers (31) spatially separated from each other by respective electrically insulating layers (32), at least some of said electrically insulating layers comprising conductive portions (33) that electrically interconnect portions of adjacent metal layers, wherein at least one of the patterned metallization layers comprises a plurality of ion-sensitive electrodes (34), each ion-sensitive electrode being electrically connected to at least one of said circuit elements, a plurality of sample volumes (50) extending into said metallization stack, each sample volume terminating at one of said ion-sensitive electrodes; and an ion-sensitive layer lining at least the ion-sensitive electrodes in said sample volumes.

Abstract: Disclosed is an integrated circuit (IC) comprising a substrate (10) carrying a plurality of circuit elements; a metallization stack (12, 14, 16) interconnecting said circuit elements, said metallization stack comprising a patterned upper metallization layer comprising at least one sensor electrode portion (20) and a bond pad portion (22), at least the at least one sensor electrode portion of said patterned upper metallization layer being covered by a moisture barrier film (23); a passivation stack (24, 26, 28) covering the metallization stack, said passivation stack comprising a first trench (32) exposing the at least one sensor electrode portion and a second trench (34) exposing the bond pad portion; said first trench being filled with a sensor active material (36). A method of manufacturing such an IC is also disclosed.

Abstract: A method of forming a pattern in at least one device layer in or on a substrate comprises: coating the device layer with a first photoresist layer; exposing the first photoresist using a first mask; developing the first photoresist layer to form a first pattern on the substrate; coating the substrate with a protection layer; treating the protection layer to cause a change therein where it is in contact with the first photoresist, to render the changed protection layer substantially immune to a subsequent exposure and/or developing step; coating the substrate with a second photoresist layer; exposing the second photoresist layer using a second mask; and developing the second photoresist layer to form a second pattern on the substrate without significantly affecting the first pattern in the first photoresist layer, wherein the first and second patterns together define interspersed features having a spatial frequency greater than that of the features defined in each of the first and second patterns separately.

Abstract: A method of forming a pattern in at least one device layer in or on a substrate comprises: coating the device layer with a first photoresist layer; exposing the first photoresist using a first mask; developing the first photoresist layer to form a first pattern on the substrate; coating the substrate with a protection layer; treating the protection layer to cause a change therein where it is in contact with the first photoresist, to render the changed protection layer substantially immune to a subsequent exposure and/or developing step; coating the substrate with a second photoresist layer; exposing the second photoresist layer using a second mask; and developing the second photoresist layer to form a second pattern on the substrate without significantly affecting the first pattern in the first photoresist layer, wherein the first and second patterns together define interspersed features having a spartial frequency greater than that of the features defined in each of the first and second patterns separately.