Abstract: Circuits and methods for a differential signal interface for coupling differential signals at a first frequency on a pair of opposite polarity signals to a multiple gigabit transceiver with generic buffers for receiving, transmitting or transceiving out of band signals at a second frequency lower than the first frequency are disclosed. Termination networks are provided coupling generic input buffers to respective ones of the pair of opposite polarity signals for receiving out of band signals where the opposite polarity signals are placed at voltages so that the differential voltage between them is below a threshold voltage. Methods for providing generic buffers with multiple gigabit transceivers for receiving and transmitting out of band signals on a differential signal interface are provided. Out of band signals are received when the out of band signaling protocol is not known.

Abstract: Circuits and methods for a differential signal interface for coupling differential signals at a first frequency on a pair of opposite polarity signals to a multiple gigabit transceiver with generic buffers for receiving, transmitting or transceiving out of band signals at a second frequency lower than the first frequency are disclosed. Termination networks are provided coupling generic input buffers to respective ones of the pair of opposite polarity signals for receiving out of band signals where the opposite polarity signals are placed at voltages so that the differential voltage between them is below a threshold voltage. Methods for providing generic buffers with multiple gigabit transceivers for receiving and transmitting out of band signals on a differential signal interface are provided. Out of band signals are received when the out of band signaling protocol is not known.

Abstract: Method and apparatus for true random number generation is described. One aspect of the invention relates to a digital logic circuit that includes N logic gates, where N is an integer greater than two. For each logic gate in the N logic gates: a first input terminal thereof is coupled to an output terminal thereof; a second input terminal thereof is coupled to an output terminal of a left neighbor thereof; and a third input terminal thereof is coupled to an output terminal of a right neighbor thereof. A sampling logic circuit may be provided to sample the output of the N logic gates to produce N-bit binary numbers. The N-bit binary numbers are true random numbers produced using pure digital logic without using an external source of randomness. A linear hybrid cellular automaton (LHCA) may be provided for scrambling output data of the sampling circuit.

Abstract: Method and apparatus for data sampling is described. More particularly, a data sampling circuit having a delay line and a plurality of tap circuits is used to sample data and provide a vector indicative of a transition region of a sampled input signal. Additionally, a hybrid sampling circuit is described with a fine grain delay line and coarse grain delay lines. Furthermore, a controller is described for using such a vector to control which data samples are used.