Abstract: An integrated circuit including a first input for receiving a scan enable control signal and a second input for receiving a test mode control signal. The integrated circuit also includes a programmable scan circuit coupled to the first input and the second input. The programmable scan circuit configures the integrated device to operate in a default mode, a scan mode, or a test mode in response to the scan enable and test mode control signals.

Abstract: A circuit including a register coupled to a control circuit. The register has a synchronous mode of operation and an asynchronous mode of operation. The a control circuit controls whether the register operates in the synchronous mode or the asynchronous mode. The circuit may further include a scan register having scan data. The control circuit may cause the register to operate in the synchronous or asynchronous mode in response to the scan data.

Abstract: A circuit for delaying a signal. The circuit includes a scan register, a logic circuit, and a programmable delay circuit. The scan register stores scan data and the logic circuit selectively decodes the scan data. The programmable delay circuit is coupled to the logic circuit and delays a signal a programmable amount of time in response to the decoded scan data.

Abstract: Method and apparatus for controlling an output transistor in an output driver circuit. In one embodiment of the invention, an input signal is routed to a first gate body which is disposed over a first channel region in a substrate. The first gate body has a first resistance to the input signal and delays the input signal through the first gate body to provide a delayed input signal. This delayed input signal is routed to a second gate body which is disposed over a second channel region in the substrate. The first gate body is coupled to the second gate body to provide the delayed input signal to the second gate body. According to one embodiment of the invention, the transistor includes the first gate body coupled to an input signal and coupled to the second gate body to receive the input signal through the first resistance of the first gate body.

Abstract: A sense amplifier circuit having a pair of complementary inputs and a pair of complementary outputs with voltage swing limiter and cross-coupled feedback to tail devices. The sense amplifier circuit comprises first differential amplifier for receiving the pair of complementary inputs to generate first output of the pair of complementary outputs. The first differential amplifier is coupled to a first current source device for biasing. The circuit also comprises second differential amplifier for receiving the pair of complementary inputs to generate second output of the pair of complementary outputs. The second differential amplifier is coupled to a second current source device for biasing. A voltage swing limiter is coupled to the pair of complementary outputs of the first and second differential amplifiers for limiting the voltage swing of the pair of complementary outputs. A feedback circuit is coupled to feed the outputs back to drive the other tail device.

Abstract: A differential latch sense amplifier for memories has (a) a first differential input circuit for detecting and shifting the voltage levels of the first and second input signals and coupled to first and second sense nodes, (b) a cross-coupled latch for providing gain to the first and second sense nodes, (c) a precharge circuit for precharging and equalizing the first and second sense nodes, (d) a first tristatable output driver for providing a first feedback, for outputting the voltage of the first sense node to a first output node, and for receiving data, (e) a second tristatable output driver for providing a second feedback, for outputting the voltage of the second sense node to a second output node, and for receiving data, and (f) a first feedback circuit for increasing the voltage gain and decreasing the sense output response time at the first and second sense nodes and for being controlled by the first and second tristatable output drivers.

Abstract: A memory includes a memory array and a decoder. The memory array includes a plurality of memory locations and the decoder is coupled to receive an address for decoding the address to generate a select signal for selecting one of the plurality of memory locations in the memory array for a memory operation. The memory further includes circuitry coupled to the decoder for delaying the select signal for a first predetermined delay time to generate a delayed select signal and for selectively applying one of the select signal and the delayed select signal to the memory array. The circuitry applies the delayed select signal to the memory array during the memory operation before the select signal is to be deasserted such that address hold time of the memory operation is decreased without affecting the memory operation.

Abstract: An apparatus and method for implementing flexible redundancy memory block elements in a divided array architecture scheme. The apparatus comprising the plurality of memory sub-arrays. Each of the memory sub-arrays includes a plurality of memory blocks having unique addresses and at least one redundancy memory block having a programmable element. Each of the memory sub-arrays is coupled to a plurality of global wordlines which are not uniquely addressed. The memory sub-arrays, namely the memory and redundancy memory blocks, are coupled to a true global read bus to allow the redundancy memory in one memory sub-array to be shared by another sub-array. The method comprises the steps needed to practice the present invention.

Abstract: A testing circuit for reading and writing a greater number of data bits in parallel during a single clock cycle than through I/O data pins in a memory device. The testing circuit comprises at least one data-in buffer, a plurality of write buffers coupled to the data-in buffer, a plurality of write buses corresponding with the plurality of write buffers and coupled therewith, a plurality of read buses to retrieve data from a plurality of memory cells, a plurality of output buffers corresponding in number with the plurality of read buses and coupled therewith and at least one output driver. Additionally, the method of testing memory basically comprises the steps of inputting at least one data bit having the predetermined polarity into the memory device in order to produce a plurality of data bits having the predetermined polarity. These plurality of data bits are written in parallel into a plurality of memory cells.

Abstract: A sense amplifier circuit having a pair of complementary inputs and a pair of complementary outputs with voltage swing limiter and cross-coupled feedback to tail devices. The sense amplifier circuit comprises first differential amplifier for receiving the pair of complementary inputs to generate first output of the pair of complementary outputs. The first differential amplifier is coupled to a first current source device for biasing. The circuit also comprises second differential amplifier for receiving the pair of complementary inputs to generate second output of the pair of complementary outputs. The second differential amplifier is coupled to a second current source device for biasing. A voltage swing limiter is coupled to the pair of complementary outputs of the first and second differential amplifiers for limiting the voltage swing of the pair of complementary outputs. A feedback circuit is coupled to feed the outputs back to drive the other tail device.

Abstract: A circuit which responds to the application of a pulse to its input (6) by generating a pulse at its output (3), the output pulse having a minimum duration T and being extended by the remaining length of the input pulse should the input pulse be still present at the end of the time T, comprises a pair of semiconductor switches (1,2) connecting the output (3) to points (5,4) carrying respective logic levels. The input pulse closes the first switch (1) and also inhibits a gate circuit (9). The resulting logic level on the output (3) closes the second switch (2) after delay by T in a delay circuit (13) and transmission through the gate circuit (9), thereby restoring the original logic level. The instant when this occurs coincides with the presence of the delayed output pulse at the output (14) of the delay circuit and the absence of the pulse at the arrangement input (6). A hold circuit circuit (15) may be provided for holding the logic level currently present at the output (3).

Abstract: An addressable memory unit has address input buffer circuits which output a pair of output connections on which, in read or write mode, two signals which are complementary to one another are present but which may also adopt equal values in such a manner as to cause a predecoder and line selector to select all or none of the selection lines controlling the cells of the memory accessed.

Abstract: When using a laser programmable fuse, a circuit should be 100% stable both before and after the fuse is blown. So far no CMOS circuit can be 100% stable without drawing a constant current. With the "Master fuse Enable" scheme one fuse circuit (master fuse) draws current while disabling all other fuse circuits on-chip. Thus giving 100% stability and reducing power consumption on a chip where no fusing has been done. If, however, one wished to use the rest of the fuses, then the master fuse is blown and all fuse circuits now become active and draw current.

Abstract: An integrated circuit having logic circuits and a logic output buffer, which circuit includes the following sub-circuits: a memory circuit and a logic output circuit, in which no tri-state occurs at the output during a sequence of data signals at the input, wherein the drive of the circuit by means of control signals is not critical over time because the first data signal from the sequence switches off the tri-state mode, the tri-state mode again being introduced if a control signal is furnished, and in the absence of this control signal, the last data signal is retained.

Abstract: A static RAM memory is optimized for speed. The memory is divided into major memory matrices and each major memory matrix is divided into memory blocks. The memory blocks are divided in groups that per group have address bits in common, which however are per group coupled to separate pads or sets of pads. These pads are interconnected on the package to common package pins.

Abstract: An integrated matrix memory includes standard sub-blocks and a redundant block. Each of the standard sub-blocks has a fixed number of standard sub-blocks, and the redundant block has one or more redundant sub-blocks. For addressing there is provided a detector for the address of a faulty standard sub-block. In that case a redundant sub-block is selected. Selection is realized by way of a sub-bus which forms part of the data path. Thus, a redundant system is achieved in which delay is minimized.

Abstract: Random access memory unit having a plurality of test modes, which is constructed as an integrated circuit and which does not include specific input/output pins to define and to command the passage to test mode. This unit is equipped with means (1) for detecting whether a predefined sequence of logic signals, which is not contained, within a set of sequences which are normally used, but the voltages of which are nevertheless included within the range of voltages which are specified for such signals, is supplied to certain inputs (CE, WE, AO), and for placing the unit in-test mode when such a sequence has been detected. In order to define the nature of the test to be performed, address input terminals, (A1-A8) of the unit are connected to a test mode decoding circuit (2), in which the data applied to the said input terminals are used as data defining the nature of the test to be performed.

Abstract: Data are frequently transmitted via a dual bus line by means of differential signals which are evaluated by a differential amplifier, particularly for reasons of protection against interference. However, such a differential amplifier only has a limited input voltage range, or a dead voltage range of the input signals within which it is not capable of operating. To prevent the voltages on both bus lines from getting into this dead voltage range, either due to a common-mode interference signal on the bus lines or due to a voltage dip in the feed voltage of the differential amplifier, the two bus lines are connected in accordance with the invention to an adjusting circuit which changes the voltages of both bus lines by the same amount in the direction out of the dead voltage range. This prevents unspecified conditions of the differential amplifier without significantly influencing the differential signal on the two bus lines. The application for an integrated memory is described.

Abstract: A push-pull output circuit which is powered by a 5-V supply voltage and in which the "push" part comprises a PMOS transistor and the "pull" comprises a PMOS transistor and an NMOS transistor. The NMOS transistor is driven via a detection circuit so that no hot carrier stress occurs in the NMOS transistor.

Abstract: A memory incorporates redundancy in the form of one or more redundant columns. An applied binary address is first distributed between predecoders which form a 1-out-of-2.sup.n code from n bits received. For each non-redundant column there is available a part of a main decoder, each part receiving a different combination of the bits supplied by the predecoders, thus selecting the column. For each redundant column there is provided a redundancy decoder. The latter decoder receives all bits supplied by the predecoders, each time via a series connection of a activatable gating element and a fuse element. Per predecoder the outputs of the series connections are combined in a wired logic function. Each wired logic function forms an input signal of the actual redundancy decoder. When a redundant column is to be addressed, all fuse elements but one of a group are opened and the gating elements are activated. A memory column to be replaced is then uncoupled by way of another fuse element.