Patents by Inventor Catharina Pusch

Catharina Pusch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6664167
    Abstract: A memory having a memory cell formed in a substrate and including a trench capacitor and a transistor and a method for producing the memory includes connecting the trench capacitor to the transistor with a self-aligned connection. The transistor at least partly covers the trench capacitor. The trench capacitor is filled with a conductive trench filling and an insulating covering layer is situated on the conductive trench filling. An epitaxial layer is situated above the insulating covering layer. The transistor is formed in the epitaxial layer. The self-aligned connection is formed in a contact trench and includes an insulation collar in which a conductive material is introduced. A conductive cap is formed on the conductive material.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: December 16, 2003
    Assignee: Infineon Technologies AG
    Inventors: Dietmar Temmler, Herbert Benzinger, Wolfram Karcher, Catharina Pusch, Martin Schrems, Jürgen Faul
  • Patent number: 6605487
    Abstract: A method for the manufacture of micro-mechanical components from a stack of layers having at least a substrate, a sacrificial layer and a layer which is to be undercut includes forming at least one etch hole in the layer, which is to be undercut, and providing at least one passivation layer for controlling a selective depositing of a cover material which closes each of the etch holes after a step of etching the sacrificial layer. The passivation layer makes it possible that the undercut layer elements do not become excessively thick or grow together with the substrate due to the deposition of the cover material.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: August 12, 2003
    Assignee: Infineon Technologies Aktiengesellschaft
    Inventors: Martin Franosch, Reinhard Wittmann, Catharina Pusch
  • Publication number: 20020137278
    Abstract: A memory having a memory cell formed in a substrate and including a trench capacitor and a transistor and a method for producing the memory includes connecting the trench capacitor to the transistor with a self-aligned connection. The transistor at least partly covers the trench capacitor. The trench capacitor is filled with a conductive trench filling and an insulating covering layer is situated on the conductive trench filling. An epitaxial layer is situated above the insulating covering layer. The transistor is formed in the epitaxial layer. The self-aligned connection is formed in a contact trench and includes an insulation collar in which a conductive material is introduced. A conductive cap is formed on the conductive material.
    Type: Application
    Filed: February 28, 2002
    Publication date: September 26, 2002
    Inventors: Dietmar Temmler, Herbert Benzinger, Wolfram Karcher, Catharina Pusch, Martin Schrems, Jurgen Faul
  • Publication number: 20020086455
    Abstract: A method for the manufacture of micro-mechanical components from a stack of layers having at least a substrate, a sacrificial layer and a layer which is to be undercut includes forming at least one etch hole in the layer, which is to be undercut, and providing at least one passivation layer for controlling a selective depositing of a cover material which closes each of the etch holes after a step of etching the sacrificial layer. The passivation layer makes it possible that the undercut layer elements do not become excessively thick or grow together with the substrate due to the deposition of the cover material.
    Type: Application
    Filed: December 20, 2001
    Publication date: July 4, 2002
    Inventors: Martin Franosch, Reinhard Wittmann, Catharina Pusch
  • Patent number: 6326262
    Abstract: A method of fabricating an epitaxial layer includes providing a substrate having a substrate surface with an at least partly uncovered monocrytalline region, and at least one electrically insulating region adjoining the monocrystalline region and being at least partly surrounded by the monocrystalline region. An epitaxial layer is grown on the monocrystalline region. The electrically insulating region is at least partly overgrown laterally with the epitaxial layer, thereby forming an epitaxial closing joint above the electrically insulating region due to the overgrowth. The epitaxial layer is at least partly removed above the electrically insulating region, thereby the epitaxial closing joint is at least partly removed.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: December 4, 2001
    Assignee: Infineon Technologies AG
    Inventors: Dietmar Temmler, Herbert Benzinger, Wolfram Karcher, Catharina Pusch, Martin Schrems, Jürgen Faul