Abstract: Methods, systems, and apparatus described herein make a multi-level PAM signal (PAM-N signal) at a transmitter using CMOS-based components. By forming the PAM-N signal at the transmitter, receivers do not have to recombine and/or realign multiple signals and only employs a single transmission line channel (or two transmission line channels in differential implementations) to convey the data stream to the receiver from the transmitter.

Abstract: Methods, systems, and apparatus described herein make a multi-level PAM signal (PAM-N signal) at a transmitter using CMOS-based components. By forming the PAM-N signal at the transmitter, receivers do not have to recombine and/or realign multiple signals and only employs a single transmission line channel (or two transmission line channels in differential implementations) to convey the data stream to the receiver from the transmitter.

Abstract: Some examples described herein provide for an integrated circuit including a continuous time linear equalizer (CTLE) circuit and a method of operating the integrated circuit. In an example, an integrated circuit includes a transconductance amplifier stage and a transimpedance amplifier stage. The transconductance amplifier stage has a first input node and a first output node. The transconductance amplifier stage includes a first complementary device inverter. The transimpedance amplifier stage has a second input node and a second output node. The first output node is electrically connected to the second input node. The transimpedance amplifier stage includes a second complementary device inverter.

Abstract: Methods, systems, and apparatus described herein make a multi-level PAM signal (PAM-N signal) at a transmitter using CMOS-based components. By forming the PAM-N signal at the transmitter, receivers do not have to recombine and/or realign multiple signals and only employs a single transmission line channel (or two transmission line channels in differential implementations) to convey the data stream to the receiver from the transmitter.

Abstract: A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit includes an injection locked oscillator, a loop controller, and a phase interpolator. The injection locked oscillator includes an input for receiving an injected clock signal and an output for forwarding a set of fixed clock phases. The loop controller includes an input for receiving a phase separation error of the fixed clock phases and an output for forwarding a supply voltage derived from the phase separation error. The supply voltage matches the free running frequency of the injection locked oscillator to a frequency of the injected clock signal. The phase interpolator includes an input for receiving the set of fixed clock phases directly from the injection locked oscillator, an input for receiving the supply voltage from the loop controller, and an output for forwarding an arbitrary clock phase.

Abstract: The phase interpolator comprises a first charge pump configured to receive a first differential clock signal having a first clock phase, wherein the first charge pump has a first current path and a second current path coupled between a first pull-up current source and a first pull-down current source, wherein the first current path comprises a first NMOS steering switch coupled between a first output node and the first pull-down current source and the second current path comprises a second NMOS steering switch coupled between a second output node and the first pull-down current source; and a second charge pump configured to receive a second differential clock signal having a second clock phase, wherein the second charge pump has a third current path and a fourth current path coupled between a second pull-up current source and a second pull-down current source, and wherein the third current path comprises a third NMOS steering switch coupled between the first output node and the second pull-down current source

Abstract: A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit includes an injection locked oscillator, a loop controller, and a phase interpolator. The injection locked oscillator includes an input for receiving an injected clock signal and an output for forwarding a set of fixed clock phases. The loop controller includes an input for receiving a phase separation error of the fixed clock phases and an output for forwarding a supply voltage derived from the phase separation error. The supply voltage matches the free running frequency of the injection locked oscillator to a frequency of the injected clock signal. The phase interpolator includes an input for receiving the set of fixed clock phases directly from the injection locked oscillator, an input for receiving the supply voltage from the loop controller, and an output for forwarding an arbitrary clock phase.

Abstract: A phase interpolator implemented in an integrated circuit to generate a clock signal is described. The phase interpolator comprises a plurality of inputs coupled to receive a plurality of clock signals; a plurality of transistor pairs, each transistor pair having a first transistor coupled to a first output node and a second transistor coupled to a second output node, wherein a first clock signal associated with the transistor pair is coupled to a gate of the first transistor and an inverted first clock signal associated with the transistor pair is coupled to a gate of the second transistor; a first active inductor load coupled to the first output node; and a second active inductor load coupled to the second output node.

Abstract: A driver apparatus is provided for controlling a light source array comprising at least first and second light sources, the light source array used for illuminating a scan region on a target object, wherein light reflected from said target object is captured by a detector. The driver apparatus comprises a single integrated circuit comprising processing means for processing image data received from the detector, a switching array comprising at least first and second switches for switching the respective first and second light sources, and a current source for controlling the flow of current through the light sources. In this way the LED switching circuitry that controls an LED array is 15 placed on the same integrated circuit (i.e. monolithic circuit) as the analogue processing circuitry that processes the image data, with the current source controlling the flow of current through the LEDs in the LED array.

Abstract: A light source is protected by selectively coupling a shunt path in parallel with the light source, such that current is diverted away from the light source and through the shunt path. A detection circuit detects the current flowing in the shunt path when the shunt path is connected in parallel with the light source. A comparator determines whether the current flowing in the shunt path exceeds a predetermined threshold and, if so, prevents or limits the flow of current when the shunt path is disconnected from being in parallel with the light source. In this way, a current detector is provided for monitoring the flow of current in a shunt path, the current detector being configured to disable or limit the flow of current through a light source when a predetermined threshold is reached.

Abstract: A driver apparatus is provided for controlling a light source array comprising at least first and second light sources, the light source array used for illuminating a scan region on a target object, wherein light reflected from said target object is captured by a detector. The driver apparatus comprises a single integrated circuit comprising processing means for processing image data received from the detector, a switching array comprising at least first and second switches for switching the respective first and second light sources, and a current source for controlling the flow of current through the light sources. In this way the LED switching circuitry that controls an LED array is placed on the same integrated circuit (i.e. monolithic circuit) as the analogue processing circuitry that processes the image data, with the current source controlling the flow of current through the LEDs in the LED array.

Abstract: A light source is protected by selectively coupling a shunt path in parallel with the light source, such that current is diverted away from the light source and through the shunt path. A detection circuit detects the current flowing in the shunt path when the shunt path is connected in parallel with the light source. A comparator determines whether the current flowing in the shunt path exceeds a predetermined threshold and, if so, prevents or limits the flow of current when the shunt path is disconnected from being in parallel with the light source. In this way, a current detector is provided for monitoring the flow of current in a shunt path, the current detector being configured to disable or limit the flow of current through a light source when a predetermined threshold is reached.