Patents by Inventor Catherine Chen
Catherine Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11953981Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.Type: GrantFiled: January 3, 2023Date of Patent: April 9, 2024Assignee: Rambus Inc.Inventors: Thomas J. Giovannini, Catherine Chen, Scott C. Best, John Eric Linstadt, Frederick A. Ware
-
Publication number: 20240095198Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.Type: ApplicationFiled: October 3, 2023Publication date: March 21, 2024Inventors: Thomas J. Giovannini, John Eric Linstadt, Catherine Chen
-
Publication number: 20230366883Abstract: The present invention provides an immunodiagnostic test device for the detection of anti-dengue virus antibodies comprising a first dengue antigen and a second dengue antigen, wherein the first dengue antigen comprises a polypeptide having at least 90% sequence identity to SEQ ID NO. 1 and the second dengue antigen comprises a polypeptide having the sequence of SEQ ID NO. 2 or a polypeptide having a sequence which has at least 1 and no more than 4 amino acid substitutions with respect to the sequence of SEQ ID NO. 2.Type: ApplicationFiled: April 5, 2023Publication date: November 16, 2023Inventors: Yasemin Ataman-Onal, Matthew Bonaparte, Catherine Chen, Vasco Liberal, Qilin Pan, Stephen Savarino, Wushan Yin, Lingyi Zheng
-
Patent number: 11809345Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.Type: GrantFiled: February 22, 2022Date of Patent: November 7, 2023Assignee: Rambus Inc.Inventors: Thomas J. Giovannini, John Eric Linstadt, Catherine Chen
-
Publication number: 20230305915Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.Type: ApplicationFiled: January 3, 2023Publication date: September 28, 2023Inventors: Thomas J. GIOVANNINI, Catherine CHEN, Scott C. BEST, John Eric LINSTADT, Frederick A. WARE
-
Publication number: 20230298642Abstract: In a memory system having multiple memory sockets for removable insertion of memory modules therein, off-module data buffers are disposed in a data signaling data path between a memory control component and the memory sockets, and an off-module buffer controller is disposed in a control signaling path between the memory control component and the memory sockets. The off-module buffer controller receives control signals transmitted by the memory control component and re-drives/re-transmits the control signals to the memory sockets. The off-module buffer controller generates buffer-control signals in response to the control signals and outputs the buffer-control signals to the off-module data buffers to multiplex host-control-component access to the memory sockets.Type: ApplicationFiled: August 24, 2021Publication date: September 21, 2023Inventors: Torsten Partsch, Shahram Nikoukary, Catherine Chen
-
Publication number: 20230188145Abstract: A phase-locked loop or delay locked loop provides a coarse alignment between an input clock and an output clock. A latch receiver circuit provides an indicator of a delay error between the input clock and the output clock. The delay error is used by a control circuit or state machine to adjust a fine delay that affects the output clock signal timing relative to the input clock signal. The fine delay is adjusted to minimize the timing difference between the output clock signal and the input clock signal.Type: ApplicationFiled: November 29, 2022Publication date: June 15, 2023Inventors: Panduka WIJETUNGA, Catherine CHEN
-
Patent number: 11573849Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.Type: GrantFiled: April 21, 2021Date of Patent: February 7, 2023Assignee: Rambus Inc.Inventors: Thomas J. Giovannini, Catherine Chen, Scott C. Best, John Eric Linstadt, Frederick A. Ware
-
Publication number: 20220245073Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.Type: ApplicationFiled: February 22, 2022Publication date: August 4, 2022Inventors: Thomas J. Giovannini, John Eric Linstadt, Catherine Chen
-
Patent number: 11275702Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.Type: GrantFiled: September 15, 2020Date of Patent: March 15, 2022Assignee: Rambus Inc.Inventors: Thomas J. Giovannini, John Eric Linstadt, Catherine Chen
-
Publication number: 20210303383Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.Type: ApplicationFiled: April 21, 2021Publication date: September 30, 2021Inventors: Thomas J. GIOVANNINI, Catherine CHEN, Scott C. BEST, John Eric LINSTADT, Frederick A. WARE
-
Patent number: 11068161Abstract: In a memory module having a plurality of discrete memory die packages, an N-bit data interface and a command/address buffer, a memory access command and chip-select input signals are received within the command/address buffer. In response to the chip-select input signals, the command/address buffer outputs chip-select output signals greater in quantity than the chip-select input signals to exclusively enable one of a plurality of groups of the discrete memory die packages to respond to the memory access command, each of the plurality of groups of the discrete memory die packages having a collective data interface width less than the N-bit data interface width.Type: GrantFiled: July 10, 2017Date of Patent: July 20, 2021Assignee: Rambus Inc.Inventors: Catherine Chen, Thomas J. Giovannini, John Eric Linstadt
-
Patent number: 11016837Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.Type: GrantFiled: November 7, 2018Date of Patent: May 25, 2021Assignee: Rambus, Inc.Inventors: Thomas J. Giovannini, Catherine Chen, Scott C. Best, John Eric Linstadt, Frederick A. Ware
-
Publication number: 20210049119Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.Type: ApplicationFiled: September 15, 2020Publication date: February 18, 2021Inventors: Thomas J. Giovannini, John Eric Linstadt, Catherine Chen
-
Patent number: 10789185Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.Type: GrantFiled: September 12, 2017Date of Patent: September 29, 2020Assignee: Rambus Inc.Inventors: Thomas J. Giovannini, John Eric Linstadt, Catherine Chen
-
Publication number: 20190179690Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.Type: ApplicationFiled: November 7, 2018Publication date: June 13, 2019Inventors: Thomas J. GIOVANNINI, Catherine CHEN, Scott C. BEST, John Eric LINSTADT, Frederick A. WARE
-
Patent number: 10146608Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.Type: GrantFiled: April 4, 2016Date of Patent: December 4, 2018Assignee: Rambus Inc.Inventors: Thomas J. Giovannini, Catherine Chen, Scott C. Best, John Eric Linstadt, Frederick A. Ware
-
Patent number: 10125112Abstract: Disclosed are modulators of the human relaxin receptor 1, for example, of formula (I), wherein A, R1, and R2 are as defined herein, that are useful in treating mammalian relaxin receptor 1 mediated facets of human health, e.g., cardiovascular disease. Also disclosed is a composition comprising a pharmaceutically suitable carrier and at least one compound of the disclosure, and a method for therapeutic intervention in a facet of mammalian health that is mediated by a human relaxin receptor 1.Type: GrantFiled: August 25, 2016Date of Patent: November 13, 2018Assignees: THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY, DEPARTMENT OF HEALTH AND HUMAN SERVICES, THE FLORIDA INTERNATIONAL UNIVERSITY BOARD OF TRUSTEESInventors: Juan Jose Marugan, Jingbo Xiao, Marc Ferrer-Alegre, Catherine Chen, Noel Southall, Wei Zheng, Alexander Agoulnik, Irina Agoulnik
-
Publication number: 20180081833Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.Type: ApplicationFiled: September 12, 2017Publication date: March 22, 2018Inventors: Thomas J. Giovannini, John Eric Linstadt, Catherine Chen
-
Patent number: D947283Type: GrantFiled: February 11, 2020Date of Patent: March 29, 2022Inventor: Catherine Chen