Abstract: In a telecommunication system adapted to exchange n-bit frames according to a dynamic time division multiplexing access method for a maximum of N accessible channels, the use of a shadow time slot assignment table is eliminated by use of a circuit that includes (a) an n×p memory block to store a time slot assignment table which describes the different time slot assignments by specifying which logical channel each bit position of an n-bit frame belongs to, (b) a register having N fields with a granularity of one bit, each bit indicates the status of the corresponding logical channel associated thereto, and (c) a logic circuit connected to the memory block and register that enables or disables the transmission of the logical channel identifier to a time slot assignor depending on the status bit value.

Abstract: In a telecommunication system adapted to exchange n-bit frames according to a dynamic time division multiplexing access method for a maximum of N accessible channels, the use of a shadow time slot assignment table is eliminated by use of a circuit that includes (a) an n×p memory block to store a time slot assignment table which describes the different time slot assignments by specifying which logical channel each bit position of an n-bit frame belongs to, (b) a register having N fields with a granularity of one bit, each bit indicates the status of the corresponding logical channel associated thereto, and (c) a logic circuit connected to the memory block and register that enables or disables the transmission of the logical channel identifier to a time slot assignor depending on the status bit value.

Abstract: In a telecommunication system adapted to exchange n-bit frames according to a dynamic time division multiplexing access method for a maximum of N accessible channels, the use of a shadow time slot assignment table is eliminated by use of a circuit that includes (a) an n×p memory block to store a time slot assignment table which describes the different time slot assignments by specifying which logical channel each bit position of an n-bit frame belongs to, (b) a register having N fields with a granularity of one bit, each bit indicates the status of the corresponding logical channel associated thereto, and (c) a logic circuit connected to the memory block and register that enables or disables the transmission of the logical channel identifier to a time slot assignor depending on the status bit value.

Abstract: The invention relates to a telecommunication system split in a plurality of subsystems that is adapted to exchange n-bit frames there between according to the dynamic time division multiplexing (TDM) access method. According to that method, the time is split in time slots, each one corresponding to one among N logical channels, wherein N is the maximum number of logical channels that can be simultaneously opened. To each logical channel (X, . . . ) is associated an identifier (LC X, . . . ) coded on p bits. In accordance with the present invention, the improved circuit (30) first comprises a n×p memory block (31) to store the time slot assignment (TSA) table which describes the different time slot assignments by specifying which logical channel each bit position of the n-bit TDM frame (Bit1 to Bitn) it belongs to.

Abstract: Each daisy chain circuit is serially connected to the two adjacent neuron circuits, so that all the neuron circuits form a chain. The daisy chain circuit distinguishes between the two possible states of the neuron circuit (engaged or free) and identifies the first free "or ready to learn" neuron circuit in the chain, based on the respective values of the input (DCI) and output (DCO) signals of the daisy chain circuit. The ready to learn neuron circuit is the only neuron circuit of the neural network having daisy chain input and output signals complementary to each other. The daisy chain circuit includes a 1-bit register (601) controlled by a store enable signal (ST) which is active at initialization or, during the learning phase when a new neuron circuit is engaged. At initialization, all the Daisy registers of the chain are forced to a first logic value.

Abstract: In a neural network comprised of a plurality of neuron circuits, an improved neuron circuit that generates local result signals, e.g. of the fire type, and a local output signal of the distance or category type. The neuron circuit which is connected to buses that transport input data (e.g. the input category) and control signals. A multi-norm distance evaluation circuit calculates the distance D between the input vector and a prototype vector stored in a R/W memory circuit. A distance compare circuit compares this distance D with either the stored prototype vector's actual influence field or the lower limit thereof to generate first and second comparison signals. An identification circuit processes the comparison signals, the input category signal, the local category signal and a feedback signal to generate local result signals that represent the neuron circuit's response to the input vector.