Patents by Inventor Catherine Graves

Catherine Graves has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210398574
    Abstract: Systems and methods for an optical ternary content addressable memory (TCAM) are provided. The optical TCAM implements a time-division multiplexing (TDM) based encoding scheme to encode each bit position of a search word in the time domain. Each bit position is associated with at least two time slots. The encoded optical signal comprising the search word is routed through one or more modulators configured to represent a respective TCAM stored word. If a mismatch between at least one bit position of the search word and at least one TCAM stored word occurs, a photodetector or photodetector array will detect light.
    Type: Application
    Filed: June 18, 2020
    Publication date: December 23, 2021
    Inventors: Thomas Van Vaerenbergh, Can Li, Catherine Graves
  • Patent number: 11200929
    Abstract: Systems and methods for an optical ternary content addressable memory (TCAM) are provided. The optical TCAM implements a time-division multiplexing (TDM) based encoding scheme to encode each bit position of a search word in the time domain. Each bit position is associated with at least two time slots. The encoded optical signal comprising the search word is routed through one or more modulators configured to represent a respective TCAM stored word. If a mismatch between at least one bit position of the search word and at least one TCAM stored word occurs, a photodetector or photodetector array will detect light.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: December 14, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Thomas Van Vaerenbergh, Can Li, Catherine Graves
  • Publication number: 20210343341
    Abstract: An analog content addressable memory cell includes a match line, a high side, and a low side. The high side encodes a high bound on a range of values and includes a first three terminal memory device. The first three terminal memory device includes a first gate that sets a high voltage bound of the first three terminal memory device. Specifically, an input voltage applied at the first gate of the first memory device, if higher than the high voltage bound, turns the first memory device ON which discharges the match line. Similarly, the low side encodes a lower bound on a range of values and includes a second three terminal memory device. The second three terminal memory device includes a second gate that sets a low voltage bound of the second three terminal memory device. Specifically, an input voltage applied at the second gate of the second memory device, if lower than the low voltage bound, turns the first memory device ON which discharges the match line.
    Type: Application
    Filed: April 30, 2020
    Publication date: November 4, 2021
    Inventors: John Paul Strachan, Catherine Graves, Can Li
  • Publication number: 20210327508
    Abstract: Systems are methods are provided for implementing an analog content addressable memory (analog CAM), which is particularly structured to allow for an amount of variance (fuzziness) in its search operations. The analog CAM may search for approximate matches with the data stored therein, or matches within a defined variance. Circuitry of the analog CAM may include transistor-source lines that receive search-variance parameters, and/or data lines that receive search-variance parameters explicitly within the search input data. The search-variance parameters may include an upper bound and a lower bound that define a range of values within the allotted amount of fuzziness (e.g., deviation from the stored value). The search-variance parameters may program (using analog approaches) the analog CAM to perform searches having a modifiable restrictiveness that is tuned dynamically, as defined by the input search-variance. Thus, highly efficient hardware for complex applications involving fuzziness are enabled.
    Type: Application
    Filed: May 3, 2021
    Publication date: October 21, 2021
    Inventors: Can Li, Catherine Graves, John Paul Strachan
  • Publication number: 20210225440
    Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.
    Type: Application
    Filed: April 6, 2021
    Publication date: July 22, 2021
    Inventors: Amit S. Sharma, John Paul Strachan, Catherine Graves, Suhas Kumar, Craig Warner, Martin Foltin
  • Patent number: 11057143
    Abstract: Systems and methods for an optical ternary content addressable memory (TCAM) is provided. In various embodiments, one or more search words can be encoded in a multi-wavelength input signal. Each bit position associated with a set of wavelengths of the input signal, each wavelength corresponding to a logic value. A plurality of copies of the input signal can be coupled to an optical search engine comprising a plurality of rows of stored words. In various embodiments, the search word may be encoded in the amplitude of a single wavelength. Each bit position can be associated with a set input waveguides, and a logic value can be encoded based on whether amplitude of the associated wavelength is detected on a respective input waveguide of the set of waveguides. A mismatch of at least one bit is indicated if light is detected on an output of the optical TCAM.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: July 6, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Thomas Van Vaerenbergh, Can Li, Catherine Graves
  • Publication number: 20210201136
    Abstract: A crossbar array includes a number of memory elements. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A processor is electronically coupled to the ADC and to the DAC. The processor may be configured to determine whether division of input vector data by output vector data from the crossbar array is within a threshold value, and if not within the threshold value, determine changed data values as between the output vector data and the input vector data, and write the changed data values to the memory elements of the crossbar array.
    Type: Application
    Filed: April 30, 2018
    Publication date: July 1, 2021
    Inventors: Sai Rahul Chalamalasetti, Paolo Faraboschi, Martin Foltin, Catherine Graves, Dejan S. Milojicic, John Paul Strachan, Sergey Serebryakov
  • Patent number: 11024379
    Abstract: Systems and methods for providing write process optimization for memristors are described. Write process optimization circuitry manipulates the memristor's write operation, allowing the number of cycles in the write process is reduced. Write process optimization circuitry can include write current integration circuitry that measures an integral of a write current over time. The write optimization circuitry can also include shaping circuitry. The shaping circuitry can shape a write pulse, by determining the pulse's termination, width, and slope. The write pulse is shaped depending upon whether the target memristor device exhibits characteristics of “maladroit” cells or “adroit” cells. The pulse shaping circuitry uses the integral and measured write current to terminate the write pulse in a manner that allows the memristor, wherein having maladroit cells and adroit cells, to reach a target state.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: June 1, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Amit Sharma, John Paul Strachan, Suhas Kumar, Catherine Graves, Martin Foltin, Craig Warner
  • Patent number: 10998047
    Abstract: Systems are methods are provided for implementing an analog content addressable memory (analog CAM), which is particularly structured to allow for an amount of variance (fuzziness) in its search operations. The analog CAM may search for approximate matches with the data stored therein, or matches within a defined variance. Circuitry of the analog CAM may include transistor-source lines that receive search-variance parameters, and/or data lines that receive search-variance parameters explicitly within the search input data. The search-variance parameters may include an upper bound and a lower bound that define a range of values within the allotted amount of fuzziness (e.g., deviation from the stored value). The search-variance parameters may program (using analog approaches) the analog CAM to perform searches having a modifiable restrictiveness that is tuned dynamically, as defined by the input search-variance. Thus, highly efficient hardware for complex applications involving fuzziness are enabled.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: May 4, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Can Li, Catherine Graves, John Paul Strachan
  • Publication number: 20210125667
    Abstract: Systems and methods for providing write process optimization for memristors are described. Write process optimization circuitry manipulates the memristor's write operation, allowing the number of cycles in the write process is reduced. Write process optimization circuitry can include write current integration circuitry that measures an integral of a write current over time. The write optimization circuitry can also include shaping circuitry. The shaping circuitry can shape a write pulse, by determining the pulse's termination, width, and slope. The write pulse is shaped depending upon whether the target memristor device exhibits characteristics of “maladroit” cells or “adroit” cells. The pulse shaping circuitry uses the integral and measured write current to terminate the write pulse in a manner that allows the memristor, wherein having maladroit cells and adroit cells, to reach a target state.
    Type: Application
    Filed: October 29, 2019
    Publication date: April 29, 2021
    Inventors: AMIT SHARMA, JOHN PAUL STRACHAN, SUHAS KUMAR, CATHERINE GRAVES, MARTIN FOLTIN, CRAIG WARNER
  • Patent number: 10984860
    Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: April 20, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Amit S. Sharma, John Paul Strachan, Catherine Graves, Suhas Kumar, Craig Warner, Martin Foltin
  • Patent number: 10930348
    Abstract: A reprogrammable dot product engine ternary content addressable memory (DPE-TCAM) is provided. The DPE-TCAM comprises a TCAM crossbar array comprising a plurality of match lines and a plurality of search lines. Each search line and match line are coupled together by a memory cell. A plurality of search line drivers are configured to apply a voltage signal to the search lines representing bits of a search word. Current sensing circuitry is coupled to the output of the plurality of match lines and configured to sense a current on the match lines, the sensed current indicating whether the search word and a stored word matched and, if not, the degree of mismatch between the two words.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: February 23, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Can Li, Catherine Graves, John Paul Strachan
  • Publication number: 20210050060
    Abstract: A reprogrammable dot product engine ternary content addressable memory (DPE-TCAM) is provided. The DPE-TCAM comprises a TCAM crossbar array comprising a plurality of match lines and a plurality of search lines. Each search line and match line are coupled together by a memory cell. A plurality of search line drivers are configured to apply a voltage signal to the search lines representing bits of a search word. Current sensing circuitry is coupled to the output of the plurality of match lines and configured to sense a current on the match lines, the sensed current indicating whether the search word and a stored word matched and, if not, the degree of mismatch between the two words.
    Type: Application
    Filed: August 13, 2019
    Publication date: February 18, 2021
    Inventors: Can Li, Catherine Graves, John Paul Strachan
  • Publication number: 20210035640
    Abstract: A content addressable memory (CAM) structure is provided. The CAM comprises a plurality of CAM cells communicatively coupled to processing circuitry. A plurality of threshold switching (TS) memristors are included, each configured to connect to a one of the plurality of CAM cells, with the first end connected to the CAM cell and the second connected to a match line. A discharge transistor is included and configured to discharge any charge on the match line in response to the CAM receiving a command to perform a search.
    Type: Application
    Filed: July 30, 2019
    Publication date: February 4, 2021
    Inventors: CAN LI, CATHERINE GRAVES, JOHN PAUL STRACHAN
  • Publication number: 20210021620
    Abstract: A secondary ternary content-addressable memory (TCAM) is programmed with a new regular expression to be added to a regular expression pattern set. Incoming data strings are processed against a primary TCAM programmed with the regular expression pattern set and against the secondary TCAM in parallel. While the incoming data strings are processed against the primary TCAM and against the secondary TCAM in parallel, the regular expression pattern set is updated to add the new regular expression.
    Type: Application
    Filed: April 30, 2018
    Publication date: January 21, 2021
    Inventors: Catherine Graves, John Paul Strachan
  • Patent number: 10896731
    Abstract: A content addressable memory (CAM) structure is provided. The CAM comprises a plurality of CAM cells communicatively coupled to processing circuitry. A plurality of threshold switching (TS) memristors are included, each configured to connect to a one of the plurality of CAM cells, with the first end connected to the CAM cell and the second connected to a match line. A discharge transistor is included and configured to discharge any charge on the match line in response to the CAM receiving a command to perform a search.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: January 19, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Can Li, Catherine Graves, John Paul Strachan
  • Patent number: 10847238
    Abstract: An analog content addressable memory cell includes a high side and a low side. The high side encodes a high bound on a range of values and includes a first voltage divider formed of a first programmable resistor and a first electronically controlled variable resistor. The low side encodes a low bound on the range of values and includes a second voltage divider formed of a second programmable resistor and a second electronically controlled variable resistor.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: November 24, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Can Li, Catherine Graves, John Paul Strachan
  • Patent number: 10847224
    Abstract: Systems, devices, and methods are provided for implementing a low power and area ternary content addressable memory (TCAM). The TCAM comprises a plurality of memristor-based TCAM (mTCAM) cells, each consisting of two memristors and two transistors. The first and second memristors are connected in series, with a first end of the first memristor connected to a first data line, first end of the second memristor connected to a second data line, and the second ends of the resistors connected together at a common node. The drain of a programming transistor is connected to the common node, with the source connected to a third data line, and the gate connected to a word line. Common node is further connected to the gate of a match-line transistor, such that if a mismatch is detected common node applies a voltage to the gate to pull-down the voltage on a pre-charged match line.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: November 24, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Can Li, Catherine Graves, John Paul Strachan
  • Patent number: 10846296
    Abstract: Filters are represented as k-SAT solutions. A filter query includes a k-SAT clause having literals pertaining to variables. A ternary content-addressable memory (TCAM) has cells programmed in correspondence with the k-SAT solutions. Input column lines of the TCAM that correspond to variables to which the literals of the k-SAT clause pertain are set in accordance with inversions of the literals. Input column lines of the TCAM that correspond to variables to which no literal of the k-SAT clause pertains are set in accordance with a “don't care” state. Responsive to any output match row line of the TCAM being set, the filter query is indicated as failing to satisfy the filters. Responsive to no output match row line of the TCAM being set, the filter query is indicated as satisfying the filters.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: November 24, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: John Paul Strachan, Catherine Graves
  • Publication number: 20200312406
    Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.
    Type: Application
    Filed: March 26, 2019
    Publication date: October 1, 2020
    Inventors: Amit S. Sharma, John Paul Strachan, Catherine Graves, Suhas Kumar, Craig Warner, Martin Foltin