Patents by Inventor Catherine Graves

Catherine Graves has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200312406
    Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.
    Type: Application
    Filed: March 26, 2019
    Publication date: October 1, 2020
    Inventors: Amit S. Sharma, John Paul Strachan, Catherine Graves, Suhas Kumar, Craig Warner, Martin Foltin
  • Publication number: 20200258587
    Abstract: An analog content addressable memory cell includes a high side and a low side. The high side encodes a high bound on a range of values and includes a first voltage divider formed of a first programmable resistor and a first electronically controlled variable resistor. The low side encodes a low bound on the range of values and includes a second voltage divider formed of a second programmable resistor and a second electronically controlled variable resistor.
    Type: Application
    Filed: February 13, 2019
    Publication date: August 13, 2020
    Inventors: Can Li, Catherine Graves, John Paul Strachan
  • Publication number: 20200073755
    Abstract: A computer system includes multiple memory array components that include respective analog memory arrays which are sequenced to implement a multi-layer process. An error array data structure is obtained for at least a first memory array component, and from which a determination is made as to whether individual nodes (or cells) of the error array data structure are significant. A determination can be made as to any remedial operations that can be performed to mitigate errors of significance.
    Type: Application
    Filed: August 28, 2018
    Publication date: March 5, 2020
    Inventors: John Paul Strachan, Catherine Graves, Dejan S. Milojicic, Paolo Faraboschi, Martin Foltin, Sergey Serebryakov
  • Publication number: 20200042287
    Abstract: Disclosed techniques provide for dynamically changing precision of a multi-stage compute process. For example, changing neural network (NN) parameters on a per-layer basis depending on properties of incoming data streams and per-layer performance of an NN among other considerations. NNs include multiple layers that may each be calculated with a different degree of accuracy and therefore, compute resource overhead (e.g., memory, processor resources, etc.). NNs are usually trained with 32-bit or 16-bit floating-point numbers. Once trained, an NN may be deployed in production. One approach to reduce compute overhead is to reduce parameter precision of NNs to 16 or 8 for deployment. The conversion to an acceptable lower precision is usually determined manually before deployment and precision levels are fixed while deployed.
    Type: Application
    Filed: August 1, 2018
    Publication date: February 6, 2020
    Inventors: Sai Rahul Chalamalasetti, Paolo Faraboschi, Martin Foltin, Catherine Graves, Dejan S. Milojicic, Sergey Serebryakov, John Paul Strachan
  • Publication number: 20190370310
    Abstract: Methods for solving systems of linear equations via utilization of a vector matrix multiplication accelerator are provided. In one aspect, a method includes receiving, from a controller and by the vector matrix multiplication accelerator, an augmented coefficient matrix. The method also comprises implementing Gaussian Elimination using the vector matrix multiplication accelerator by: monitoring, by a register in at least one swap operation, a row order of the augmented coefficient matrix when a first row is swapped with a second row of the augmented coefficient matrix, delivering, by the controller in at least one multiply operation, an analog voltage to a desired row of the augmented coefficient matrix to produce a multiplication result vector, and adding, in at least one add operation, the first row to another desired row of the augmented coefficient matrix to produce an add result vector. Systems and circuits are also provided.
    Type: Application
    Filed: June 1, 2018
    Publication date: December 5, 2019
    Inventors: Catherine Graves, John Paul Strachan
  • Patent number: 10489482
    Abstract: Methods for solving systems of linear equations via utilization of a vector matrix multiplication accelerator are provided. In one aspect, a method includes receiving, from a controller and by the vector matrix multiplication accelerator, an augmented coefficient matrix. The method also comprises implementing Gaussian Elimination using the vector matrix multiplication accelerator by: monitoring, by a register in at least one swap operation, a row order of the augmented coefficient matrix when a first row is swapped with a second row of the augmented coefficient matrix, delivering, by the controller in at least one multiply operation, an analog voltage to a desired row of the augmented coefficient matrix to produce a multiplication result vector, and adding, in at least one add operation, the first row to another desired row of the augmented coefficient matrix to produce an add result vector. Systems and circuits are also provided.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: November 26, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Catherine Graves, John Paul Strachan
  • Publication number: 20190332708
    Abstract: Filters are represented as k-SAT solutions. A filter query includes a k-SAT clause having literals pertaining to variables. A ternary content-addressable memory (TCAM) has cells programmed in correspondence with the k-SAT solutions. Input column lines of the TCAM that correspond to variables to which the literals of the k-SAT clause pertain are set in accordance with inversions of the literals. Input column lines of the TCAM that correspond to variables to which no literal of the k-SAT clause pertains are set in accordance with a “don't care” state. Responsive to any output match row line of the TCAM being set, the filter query is indicated as failing to satisfy the filters. Responsive to no output match row line of the TCAM being set, the filter query is indicated as satisfying the filters.
    Type: Application
    Filed: April 30, 2018
    Publication date: October 31, 2019
    Inventors: John Paul Strachan, Catherine Graves
  • Patent number: 10452472
    Abstract: A dot-product engine (DPE) implemented on an integrated circuit as a crossbar array (CA) includes memory elements comprising a memristor and a transistor in series. A crossbar with N rows, M columns may have N×M memory elements. A vector input for N voltage inputs to the CA and a vector output for M voltage outputs from the CA. An analog-to-digital converter (ADC) and/or a digital-to-analog converter (DAC) may be coupled to each input/output register. Values representing a first matrix may be stored in the CA. Voltages/currents representing a second matrix may be applied to the crossbar. Ohm's Law and Kirchoff's Law may be used to determine values representing the dot-product as read from the crossbar. A portion of the crossbar may perform Error-correcting Codes (ECC) concurrently with calculating the dot-product results. ECC codes may be used to only indicate detection of errors, or for both detection and correction of results.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: October 22, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Catherine Graves, John Paul Strachan, Dejan S. Milojicic, Paolo Faraboschi, Martin Foltin, Sergey Serebryakov
  • Publication number: 20190284290
    Abstract: The present invention includes apoptotic compositions and methods for inducing apoptosis of cancer cells independent of NK cells. An apoptotic composition comprises a cooperative combination of antibodies that specifically bind to human DR5, or a cooperative combination of an anti-DR5 antibody and TRAIL. Administration of therapeutically effective amounts of an apoptotic composition induces apoptosis of apoptosis sensitive cancer cells.
    Type: Application
    Filed: October 31, 2018
    Publication date: September 19, 2019
    Inventors: Pamela Mary Holland, Jonathan David Graves, Jennifer Joy Kordich, Julia Catherine Piasecki, Ian Nevin Foltz
  • Patent number: 10419346
    Abstract: An input string is mapped to a vector of input voltages. The vector is applied to input rows of a dot product engine having memristor elements at intersections of the input rows and output columns. A hash of the input string is determined based on output of the dot product engine as to which the vector of input voltages have been applied to the input rows thereof. An output column may be selected from output voltages of the columns, and the hash determined from the selected column. The output voltage of a column is equal to a sum of a product of the input voltage in each input row and a value of the memristor element at the intersection of the input row and the column. The hash can be used within a filtering technique applied to the input string, such as in the context of network security.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: September 17, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT L.P.
    Inventors: John Paul Strachan, Catherine Graves, Suhas Kumar
  • Patent number: 10418103
    Abstract: According to examples, an apparatus may include a ternary content addressable memory (TCAM) including a plurality of TCAM bit cells connected in a row along a match line. Each of the TCAM bit cells may store a bit of a TCAM word and the TCAM bit cells may drive a digital signal over the match line in response to a search word matching the TCAM word. The apparatus may include a resistive random-access memory (RRAM) comprising a row of RRAM bit cells connected to the TCAM via the match line. Each of the RRAM bit cells may store a bit of a RRAM word. The RRAM bit cells may output the RRAM word in response to the TCAM bit cells driving the digital signal over the match line.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: September 17, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Brent Buchanan, John Paul Strachan, Le Zheng, Catherine Graves
  • Patent number: 10380386
    Abstract: A crossbar array includes a number of memory elements. A vector input register has N voltage inputs to the crossbar array. A vector output register has M voltage outputs from the crossbar array. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A clustering processor is electronically coupled to the ADC and to the DAC. The clustering processor is configured to program columns of the crossbar array with a set of k cluster center values; apply voltages to rows of the crossbar array where the applied voltages represent a set of data values; and determine a minimum distance of each data value to each k cluster center values based on the voltage output from the output register of each of the plurality of the programmed columns.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: August 13, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: John Paul Strachan, Catherine Graves, Suhas Kumar
  • Publication number: 20060094069
    Abstract: The invention relates to tumour marker proteins and their preparation from fluids from one or more cancer patients, wherein said fluids are those which collect in a body cavity or space which is naturally occurring or which is the result of cancer or medical intervention for cancer. The invention also relates to preparation of tumour marker proteins from excretions taken from patients with cancer. The tumour marker proteins are useful as immunoassay reagents in the detection of cancer-associated anti-tumour marker autoantibodies.
    Type: Application
    Filed: November 13, 2003
    Publication date: May 4, 2006
    Inventors: John Forsyth Robertson, Catherine Graves