Abstract: A method includes performing a first chemical mechanical polishing process to define a polished replacement gate structure having a dished upper surface, wherein the polished dished upper surface of the polished replacement gate structure has a substantially curved concave configuration. A gate cap layer is formed above the polished replacement gate structure, wherein a bottom surface of the gate cap layer corresponds to the polished dished upper surface of the polished replacement gate structure.

Abstract: A method includes performing a first chemical mechanical polishing process to define a polished replacement gate structure having a dished upper surface, wherein the polished dished upper surface of the polished replacement gate structure has a substantially curved concave configuration. A gate cap layer is formed above the polished replacement gate structure, wherein a bottom surface of the gate cap layer corresponds to the polished dished upper surface of the polished replacement gate structure.

Abstract: Antireflective residues during pattern transfer and consequential short circuiting are eliminated by employing an underlying sacrificial layer to ensure complete removal of the antireflective layer. Embodiments include forming a hard mask layer over a conductive layer, e.g., a silicon substrate, forming the sacrificial layer over the hard mask layer, forming an optical dispersive layer over the sacrificial layer, forming a silicon anti-reflective coating layer over the optical dispersive layer, forming a photoresist layer over the silicon anti-reflective coating layer, where the photoresist layer defines a pattern, etching to transfer the pattern to the hard mask layer, and stripping at least the optical dispersive layer and the sacrificial layer.

Abstract: Antireflective residues during pattern transfer and consequential short circuiting are eliminated by employing an underlying sacrificial layer to ensure complete removal of the antireflective layer. Embodiments include forming a hard mask layer over a conductive layer, e.g., a silicon substrate, forming the sacrificial layer over the hard mask layer, forming an optical dispersive layer over the sacrificial layer, forming a silicon anti-reflective coating layer over the optical dispersive layer, forming a photoresist layer over the silicon anti-reflective coating layer, where the photoresist layer defines a pattern, etching to transfer the pattern to the hard mask layer, and stripping at least the optical dispersive layer and the sacrificial layer.

Abstract: An illustrative test structure is disclosed herein that includes a plurality of first line features and a plurality of second line features. In this embodiment, each of the second line features have first and second opposing ends and the first and second line features are arranged in a grating pattern such that the first ends of the first line features are aligned to define a first side of the grating structure and the second ends of the first features are aligned to define a second side of the grating structure that is opposite the first side of the grating structure. The first end of the second line features has a first end that extends beyond the first side of the grating structure while the second end of the second line features has a first end that extends beyond the second side of the grating structure.

Abstract: An illustrative test structure is disclosed herein that includes a plurality of first line features and a plurality of second line features. In this embodiment, each of the second line features have first and second opposing ends and the first and second line features are arranged in a grating pattern such that the first ends of the first line features are aligned to define a first side of the grating structure and the second ends of the first features are aligned to define a second side of the grating structure that is opposite the first side of the grating structure. The first end of the second line features has a first end that extends beyond the first side of the grating structure while the second end of the second line features has a first end that extends beyond the second side of the grating structure.

Abstract: Antireflective residues during pattern transfer and consequential short circuiting are eliminated by employing an underlying sacrificial layer to ensure complete removal of the antireflective layer. Embodiments include forming a hard mask layer over a conductive layer, e.g., a silicon substrate, forming the sacrificial layer over the hard mask layer, forming an optical dispersive layer over the sacrificial layer, forming a silicon anti-reflective coating layer over the optical dispersive layer, forming a photoresist layer over the silicon anti-reflective coating layer, where the photoresist layer defines a pattern, etching to transfer the pattern to the hard mask layer, and stripping at least the optical dispersive layer and the sacrificial layer.

Abstract: Methods for fabricating integrated circuits using tailored chamfered gate liner profiles are provided. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a dummy gate electrode overlying a semiconductor substrate and forming a liner on sidewalls of the dummy gate electrode. A dielectric material is deposited overlying the dummy gate electrode, the liner, and the substrate. The dummy gate electrode is exposed by chemical mechanical planarization. A portion of the dummy gate electrode is removed and the liner is isotropically etched such that it has a chamfered surface. A remainder of the dummy gate electrode is removed to form an opening that is filled with a metal.

Abstract: An illustrative test structure is disclosed herein that includes a plurality of first line features and a plurality of second line features. In this embodiment, each of the second line features have first and second opposing ends and the first and second line features are arranged in a grating pattern such that the first ends of the first line features are aligned to define a first side of the grating structure and the second ends of the first features are aligned to define a second side of the grating structure that is opposite the first side of the grating structure. The first end of the second line features has a first end that extends beyond the first side of the grating structure while the second end of the second line features has a first end that extends beyond the second side of the grating structure.

Abstract: Disclosed herein are various methods of forming a gate cap layer above a replacement gate structure, and a device having such a cap layer. In one example, a device disclosed herein includes a replacement gate structure having a dished upper surface, sidewall spacers positioned proximate the replacement gate structure and a gate cap layer positioned above the replacement gate structure, wherein the gate cap layer has a bottom surface that corresponds to the dished upper surface of the replacement gate structure.

Abstract: A methodology for varying the depth of a design feature on a semiconductor wafer. Vias are formed according to design requirements. Nonfunctioning vias may also be placed at a location with respect to a design feature. After vias are formed, the semiconductor wafer is caused to undergo an ashing process followed by the application of an organic planarizing layer. The design features are then formed. If the depth of the design features does not meet design requirements, another semiconductor wafer may be processed to meet design requirements by varying the ashing conditions, choice of organic planarizing layer and/or the nonfunctioning and/or functioning via placement. Design features having various depths on a single semiconductor wafer may be formed with a single lithographic process.

Abstract: Antireflective residues during pattern transfer and consequential short circuiting are eliminated by employing an underlying sacrificial layer to ensure complete removal of the antireflective layer. Embodiments include forming a hard mask layer over a conductive layer, e.g., a silicon substrate, forming the sacrificial layer over the hard mask layer, forming an optical dispersive layer over the sacrificial layer, forming a silicon anti-reflective coating layer over the optical dispersive layer, forming a photoresist layer over the silicon anti-reflective coating layer, where the photoresist layer defines a pattern, etching to transfer the pattern to the hard mask layer, and stripping at least the optical dispersive layer and the sacrificial layer.

Abstract: A methodology for varying the depth of a design feature on a semiconductor wafer. Vias are formed according to design requirements. Nonfunctioning vias may also be placed at a location with respect to a design feature. After vias are formed, the semiconductor wafer is caused to undergo an ashing process followed by the application of an organic planarizing layer. The design features are then formed. If the depth of the design features does not meet design requirements, another semiconductor wafer may be processed to meet design requirements by varying the ashing conditions, choice of organic planarizing layer and/or the nonfunctioning and/or functioning via placement. Design features having various depths on a single semiconductor wafer may be formed with a single lithographic process.

Abstract: Prevention of damage to an interlevel dielectric (ILD) is provided by forming an opening (e.g., trench) in the ILD, and sputtering a dielectric film onto a sidewall of the opening by overetching into a layer of the dielectric below or within the ILD during forming of the opening. The re-sputtered film protects the sidewall of the opening from subsequent plasma/ash processes and seals the porous dielectric surface along the sidewall and bottom without impacting overall process throughput. A semiconductor structure resulting from the above process is also disclosed.

Abstract: Methods of de-fluorinating a wafer surface after damascene processing and prior to photoresist removal are disclosed, as is a related structure. In one embodiment, the method places the wafer surface in a chamber and exposes the wafer surface to a plasma from a source gas including at least one of nitrogen (N2) and/or hydrogen (H2) at a low power density or ion density. The exposing step removes the chemisorbed and physisorbed fluorine residue present on the wafer surface (and chamber), and improves ultra low dielectric (ULK) interconnect structure robustness and integrity. The exposing step is operative due to the efficacy of hydrogen and nitrogen radicals at removing fluorine-based species and also due to the presence of a minimal amount of ion energy in the plasma. The low power density nitrogen and/or hydrogen-containing plasma process enables negligible ash/adhesion promoter interaction and reduces integration complexity during dual damascene processing of low-k OSG-based materials.

Abstract: According to one exemplary embodiment, a method for forming a field-effect transistor on a substrate, where the substrate includes a high-k dielectric layer situated over the substrate and a gate electrode layer situated over the high-k dielectric layer, comprises a step of etching the gate electrode layer and the high-k dielectric layer to form a gate stack, where the gate stack comprises a high-k dielectric segment situated over the substrate and a gate electrode segment situated over the high-k dielectric segment. According to this exemplary embodiment, the method further comprises performing a nitridation process on the gate stack. The nitridation process can be performed by, for example, utilizing a plasma to nitridate sidewalls of the gate stack, where the plasma comprises nitrogen. The nitridation process can cause nitrogen to enter the high-k dielectric segment and form an oxygen diffusion barrier in the high-k dielectric segment, for example.