Patents by Inventor Caveh Jalali

Caveh Jalali has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7398356
    Abstract: A memory subsystem includes multiple different caches configured for different types of data transfer operations between one or more processing units and a main memory. The different caches can include a first general cache configured for general random memory accesses, a software controlled cache used for controlling cache operations for different processing devices accessing the same data, and a streaming cache configured for large packet data memory accesses. An arbiter may be used for arbitrating requests by the multiple different caches for accessing the main memory.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: July 8, 2008
    Assignee: Mistletoe Technologies, Inc.
    Inventors: Hoai V. Tran, Kevin Jerome Rowett, Somsubhra Sikdar, Jonathan Sweedler, Caveh Jalali
  • Publication number: 20070027991
    Abstract: A system and method for isolating TCP comprises a proxy configured to manage a plurality of sessions including at least one transmission control protocol session, wherein the proxy translates data between the transmission control protocol session and a local session.
    Type: Application
    Filed: July 14, 2005
    Publication date: February 1, 2007
    Applicant: Mistletoe Technologies, Inc.
    Inventors: Somsubhra Sikdar, Kevin Rowett, Caveh Jalali, Prasad Rallapalli
  • Publication number: 20070022225
    Abstract: A system and method comprising a direct memory access (DMA) circuit configured to directly access a memory, and a checksum adder configured to determine a checksum for data transferred between the DMA circuit and the memory.
    Type: Application
    Filed: July 21, 2005
    Publication date: January 25, 2007
    Applicant: Mistletoe Technologies, Inc.
    Inventors: Rajesh Nair, Komal Rathi, Caveh Jalali
  • Publication number: 20070019661
    Abstract: An embodiment of the invention is a processor comprising a direct execution parser configured to control the processing of digital data by semantically parsing data; a plurality of semantic processing units configured to perform data operations when prompted by the direct execution parser; and a plurality of output buffers for buffering data received from the plurality of semantic processing units. Another embodiment of the invention is an interface circuit comprising a packer circuit for receiving data from a semantic processing unit and a plurality of buffers for receiving the data. The interface circuit unloads the data received to an interface.
    Type: Application
    Filed: July 20, 2005
    Publication date: January 25, 2007
    Applicant: Mistletoe Technologies, Inc.
    Inventors: Kevin Rowett, Rajesh Nair, Caveh Jalali, Joel Lach
  • Publication number: 20070022479
    Abstract: A network processing device provides a novel architecture for conducting firewall and other network interface management operations. In another aspect of the invention, a Unified Policy Management (UPM) architecture uses a same memory and processing structure to integrate firewall policy management with routing and switching decisions. In another embodiment, a Reconfigurable Semantic Processor (RSP) uses a parser to identify different syntactic elements that are then used by one or more Semantic Processing Units (SPUs) to carry out different firewall, network interface, routing, switching, and other packet processing operations.
    Type: Application
    Filed: July 21, 2005
    Publication date: January 25, 2007
    Inventors: Somsubhra Sikdar, Kevin Rowett, Caveh Jalali, Steven Ellis
  • Publication number: 20060020756
    Abstract: A memory subsystem includes multiple different caches configured for different types of data transfer operations between one or more processing units and a main memory. The different caches can include a first general cache configured for general random memory accesses, a software controlled cache used for controlling cache operations for different processing devices accessing the same data, and a streaming cache configured for large packet data memory accesses. An arbiter may be used for arbitrating requests by the multiple different caches for accessing the main memory.
    Type: Application
    Filed: July 13, 2005
    Publication date: January 26, 2006
    Inventors: Hoai Tran, Kevin Rowett, Somsubhra Sikdar, Jonathan Sweedler, Caveh Jalali
  • Patent number: 6446137
    Abstract: A system and method allow client applications to invoke remote procedures on a server application using any of a plurality of remote procedure mechanisms, by selecting a remote procedure call mechanism at runtime. The system and method uses client and server stubs in the application that include an mechanism-independent canonical specification of each procedure interface. The specification defines the form of the interface and arguments, but not does include conventional mechanism-specific marshalling arguments for marshalling the arguments. The resulting compiled stubs may be used with any remote procedure call engine. Such remote procedure call engines receive the specification of the procedure interface and the arguments passed by the client application to the server, and determine at runtime the particular marshalling routines to use, according to the canonical specification.
    Type: Grant
    Filed: March 12, 1999
    Date of Patent: September 3, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Rangaswamy Vasudevan, Caveh Jalali
  • Patent number: 5887172
    Abstract: A system and method allow client applications to invoke remote procedures on a server application using any of a plurality of remote procedure mechanisms, by selecting a remote procedure call mechanism at runtime. The system and method uses client and server stubs in the application that include an mechanism-independent canonical specification of each procedure interface. The specification defines the form of the interface and arguments, but not does include conventional mechanism-specific marshalling arguments for marshalling the arguments. The resulting compiled stubs may be used with any remote procedure call engine. Such remote procedure call engines receive the specification of the procedure interface and the arguments passed by the client application to the server, and determine at runtime the particular marshalling routines to use, according to the canonical specification.
    Type: Grant
    Filed: January 10, 1996
    Date of Patent: March 23, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: Rangaswamy Vasudevan, Caveh Jalali