Abstract: A multi-chip package with a LOC lead frame is disclosed. Such a LOC lead frame has a plurality of leads, with each lead from inside to outside being divided into a first inner portion, a supporting portion, a second inner portion and an outer connecting portion. By bending the leads, the first inner portion, the supporting portion, and the second inner portion are formed on different planes. The first inner portion is sticking to the bottom chip and enables the electrical connection to the bottom chip. The supporting portion is sticking to the upper chip, while the second inner portion enables the bonding wires electrically connect the upper chip. This design can pack the upper and the bottom chips with a LOC lead frame without turnover action during wire-bonding.

Abstract: A multi-chip package with a LOC lead frame is disclosed. Such a LOC lead frame has a plurality of leads, with each lead being divided into an inner portion and an outer connecting portion. A first tape adhering under the inner portions of the leads fastens the first chip and the first bonding wires electrically connect the first chip with the inner portions. A second tape adhering upon the inner portions of the leads fastens the second chip and the second bonding wires electrically connect the second chip with the inner portions. The second tape has a thickness so as to avoid the first bonding wires touching the second chip. The multi-chip package enables to package at least two chips by a LOC lead frame without turnover action during wire-bonding.

Abstract: A multi-chip package with a LOC lead frame is disclosed. Such a LOC lead frame has a plurality of leads, with each lead from inside to outside being divided into a first inner portion, a supporting portion, a second inner portion and an outer connecting portion. By bending the leads, the first inner portion, the supporting portion, and the second inner portion are formed on different planes. The first inner portion is sticking to the bottom chip and enables the electrical connection to the bottom chip. The supporting portion is sticking to the upper chip, while the second inner portion enables the bonding wires electrically connect the upper chip. This design can pack the upper and the bottom chips with a LOC lead frame without turnover action during wire-bonding.

Abstract: A double sided chip package is disclosed. The package includes a LOC leadframe having a plurality of leads. Each lead is outwardly divided into a supporting portion extended between a bottom chip and a upper chip for supporting both chips, an inner connecting portion sealed by a package body for electrically connecting the bottom chip and the upper chip to the LOC leadframe by wire-bonging, and an outer portion exposed from the package body. So the double sided chip package has the benefits of a less warping, a stronger lead bonding, and a well-balancing molding flow.

Abstract: A multi-chip package with a LOC lead frame is disclosed. Such a LOC lead frame has a plurality of leads, with each lead being divided into an inner portion and an outer connecting portion. A first tape adhering under the inner portions of the leads fastens the first chip and the first bonding wires electrically connect the first chip with the inner portions. A second tape adhering upon the inner portions of the leads fastens the second chip and the second bonding wires electrically connect the second chip with the inner portions. The second tape has a thickness so as to avoid the first bonding wires touching the second chip. The multi-chip package enables to package at least two chips by a LOC lead frame without turnover action during wire-bonding.