Patents by Inventor Cecil James Aswell

Cecil James Aswell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6703682
    Abstract: A method and apparatus is disclosed for providing highly linear resistance with high sheet values, and for implementing resistors in a conventional CMOS process when either drain or source must operate near the rail of a circuit. Accordingly, a five terminal distributed MOS resistor device includes a drain terminal, a source terminal, and a channel region disposed between the drain terminal and the source terminal. A bulk terminal is adjacent the channel region. A first gate terminal is adjacent the source terminal and a second gate terminal is adjacent the drain terminal. Lastly, a gate region of resistive material is disposed between the first gate terminal and the second gate terminal, wherein upon application of a voltage to the first gate terminal and the second gate terminal, a voltage drop across the gate region is equally distributed along a length of an electrical channel in the channel region.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: March 9, 2004
    Assignee: Texas Advanced Optoelectronic Solutions, Inc.
    Inventor: Cecil James Aswell
  • Publication number: 20010050410
    Abstract: A method and apparatus is disclosed for providing highly linear resistance with high sheet values, and for implementing resistors in a conventional CMOS process when either drain or source must operate near the rail of a circuit. Accordingly, a five terminal distributed MOS resistor device includes a drain terminal, a source terminal, and a channel region disposed between the drain terminal and the source terminal. A bulk terminal is adjacent the channel region. A first gate terminal is adjacent the source terminal and a second gate terminal is adjacent the drain terminal. Lastly, a gate region of resistive material is disposed between the first gate terminal and the second gate terminal, wherein upon application of a voltage to the first gate terminal and the second gate terminal, a voltage drop across the gate region is equally distributed along a length of an electrical channel in the channel region.
    Type: Application
    Filed: December 21, 2000
    Publication date: December 13, 2001
    Inventor: Cecil James Aswell