Abstract: A method and apparatus for a processor of a computer system to control a communication device through a bus interface having six interconnects. The bus interface's first interconnect is a transmission and reception interconnect that allows the computer system to transmit and receive signals from a communication device (such as a telephone line or a radio transceiver). The second interconnect is a primary processor communication interconnect which serves as the primary communication route between the processor and a radio transceiver's microcontroller, and which enables the processor to control the various components of the radio transceiver. The third interconnect is a secondary processor communication interconnect that relays urgent signals (such as status, interrupt, and reset signals) between the processor and the radio transceiver's microcontroller.