Abstract: An incremental phase shifter for digital signals adapted to combine weighted amount of two quadrature square waves so as to generate a wave having a phase intermediate the respective phases of the two quadrature square wave signals. The generated wave is then processed in a limiting and integrating circuit so as to produce a square wave which is linearly related to the assigned weighted amounts of the two quadrate square waves.

Abstract: Timing recovery circuitry for recovering digital data generates a timing signal which is a function of the delay provided by an equalizer to one or more predetermined frequency components of its input signal. Advantageously, this approach is applicable to systems which utilize one or more baseband or passband equalizers. The disclosed embodiments of the present invention pertain to a dual-duplex system. In such a system, the digital data to be transmitted is divided into two different digital signals and each signal is coupled through an associated transmission channel. At the receiver, the received version of each transmitted signal is processed by an associated equalizer and the outputs therefrom are combined to recover the digital data. In the disclosed embodiments of the present invention, the necessary timing signal for such recovery is a function of the delay introduced by each equalizer to at least one predetermined frequency component of that equalizer's input signal.

Abstract: In a dual-duplex system wherein the communications channels have associated propagation delays which are typically different from one another, equalizers are connected to operate upon the signal received from each channel. To synchronize the operation of these equalizers to each other, the coefficients of each equalizer are updated when the training sequence is received from at least one of the communications channels. The sequence of symbol values in the training sequence may either be known or unknown to the receiver prior to transmission. When this sequence is detected, the coefficient updating circuit for each equalizer operates in response to a common reference signal. This reference signal includes a plurality of symbols and the value of each symbol is supplied at the same time to each equalizer coefficient updating circuit.

Abstract: A rational rate generator circuit is disclosed where the output signal frequency, f.sub.o, is rationally related to the input signal frequency, f.sub.i, by: f.sub.o =f.sub.i (P/Q). This rational rate generator is capable of a high-resolution output, where the resolution is only limited by the value of the integers P and Q, with P<Q.

Abstract: The process of interpolating between two different sampling rates at any point in a sampling interval is obtained using a transversal filter arranged as a continuously variable digital delay line in which the tap coefficients of the delay line are made to be a function of the coefficients of an nth degree polynomial and the delay between the two sampling rates.

Abstract: The computational processing power of a Digital Signal Processor (DSP) in linear-phase Finite Impulse Response Filter (FIR) applications is essentially doubled by taking advantage of either the even (symmetrical) or odd (antisymmetrical) symmetry of the response of such a filter.

Abstract: In accordance with the present invention, local loop testing in an echo canceller based modem is provided in a manner in which proper operation of both the receiver and echo canceller can be assessed simultaneously. Specifically, the modem includes means for generating data and interfering symbol sequences and for applying the interfering sequence to both the echo canceller and the modem transmitter, while applying the data sequence only to either the transmitter or the echo canceller. During closed loop testing, the modem connection to the transmission line is opened, and a portion of the output of the modem transmitter is applied to the modem receiver via a leakage path through the hybrid. The received symbol is subtracted from the echo canceller output, resulting in application to the receiver of only a version of the data symbol sequence. Advanced knowledge of the characteristics of the data symbol sequence allows proper receiver operation to be verified.

Abstract: In a data receiver employing a fractionally spaced equalizer, the phase with which samples of the received signal are formed is controlled in response to a signal indicative of the center of gravity of the equalizer coefficient.

Abstract: An adaptive equalizer for data signals is allowed to start up and train in a wholly decision-directed mode but is precluded from converging to an incorrect state by inhibiting equalizer updating for equalizer output values which fall within a predetermined null zone.

Abstract: A method and apparatus for rapid initialization of the transversal filter efficients in an echo canceler or echo measurement device is described. During initialization, a first data sequence is applied to a transmission channel, and an error signal representing the difference between the resulting echo and a replica thereof generated by the transversal filter is formed. The coefficients used to form the replica (in the case of an echo canceler) or to model the transmission channel (in the case of an echo measurement device) are then updated as a function of the error and a second data sequence which is orthogonal to the first sequence.

Abstract: Accurate recovery of constituent data streams from a multiplexed serial data stream in which each symbol includes a nonintegral number of frames is accomplished by combining a coherently detected timing signal, which is a component of the received serial data stream, together with a bit clock signal and a symbol clock signal to locate a predetermined bit position within each frame. When the location of the predetermined bit position is determined, frame synchronization is complete and the constituent data streams are correctly demultiplexed from the multiplexed serial data stream. The timing signal has a pulse rate equal to the greatest common divisor of the frame and symbol rates.

Abstract: Combined amplitude and phase modulation of a multiplexed serial data stream is employed to generate a composite signal for transmission to a receiver. The composite signal includes a prescribed timing signal identifying a predetermined bit position in at least each n.sup.th symbol and group of n.multidot.M bits in the serial data stream. The timing signal forms the amplitude modulation component of the composite signal and is utilized by the receiver for properly resolving an n-fold ambiguity which arises when each symbol includes a nonintegral rational number of frames.

Abstract: A shift-keyed modulator utilizes a lookup table (41) to provide a binary sequence of digits one at a time. Since the binary digits are selected so that their accumulation represents the amplitudes of a series of points on a theoretical sinusoidal wave, a low-pass filter (51) acting as an integrator is able to provide a sinusoidal wave signal. Furthermore, the low-pass filter includes gates that operate in push-pull fashion to form a balanced configuration for cancelling even ordered harmonic distortion. The modulator has a rate multiplier (11) responsive to space/mark signaling for controlling the rate the the binary digits are produced by the lookup table. A second group of binary digits is stored in the lookup table and is read out concurrently with the first sequence. Alternate pairs of gates (52 and 53 or 54 and 55) are enabled in the low-pass filter to provide binary data signals for either of the frequency bands used in duplex data signaling circuits.

Abstract: A digital automatic gain control (AGC) circuit in a digital communication receiver generates a gain adjusted output signal (104) having nominally constant output power by controllably attenuating an input signal (101). Attenuation is accomplished by employing a coarse analog attenuator (106, 107) and a fine digital attenuator (108) under control of a digital control circuit (60). Attenuation adjustments to the analog attenuator (106, 107) alone perturb the gain adjusted output signal (104) causing processing errors in the digital receiver. The digital attenuator (108) is controllably adjusted, in a predetermined manner, to minimize the number of subsequent adjustments made to the analog attenuator (106, 107) following a first adjustment. Adjusting the digital attenuator to a prescribed intermediate attenuation setting (G.sub.O) between predetermined maximum and minimum attenuation settings (T.sub.HI,T.sub.