Abstract: A device for protecting I/O lines using PIN or NIP low capacitance transient voltage suppressors and steering diodes are disclosed. In an exemplary embodiment, a two (2) terminal device with a unidirectional low capacitance TVS diode (1101) and an anti-parallel LC PIN or NIP diode (1102) is disclosed. To provide for a low capacitance TVS with a forward conducting low-voltage characteristic, the LC PIN or NIP diode is placed anti-parallel to the unidirectional low capacitance TVS. This LC PIN or NIP diode must also have a reverse blocking voltage greater than the avalanche breakdown p-n junction voltage (V(BR)) of the unidirectional TVS.

Abstract: A device for protecting I/O lines using low capacitance steering diodes (1200) and PIN or NIP diodes (1202), (1203) is disclosed. A low capacitance diode arrangement configured as steering diodes protect a signal line or input/output (I/O) port (1201) from high voltage transients by diverting or directing the transient to either the positive side of the power supply line (1204) or to ground (1205).

Abstract: A bi-directional low capacitance TVS using a PIN or NIP diode is disclosed. Bi-directional low capacitance TVS protection circuit (1000) consists of two pairs of TVS diodes (1001), (1003) and LC PIN or NIP diodes (1002), (1004). Diodes (1003) and (1004) are in parallel and in opposite direction from a first series of TVS and LC diode pair. This circuit provides transient protection in both directions for a bi-directional low capacitance TVS.

Abstract: Unidirectional and bi-directional low capacitance transient voltage suppressors (“TVS”) and steering diodes are disclosed. In one embodiment, the TVS comprise TVS p-n junction diode element(s), (101) low-capacitance (“LC”) PIN or NIP diode element(s) (102), the TVS p-n junction diode element(s) (101) being placed in series with and in opposite polarity to the LC PIN or NIP diodes (102). In another embodiment, the steering diode comprise only LC PIN or NIP diode(s) (402, 403) arranged as steering diodes. This circuit arrangement is operable to clamp high-voltage transients of either polarity to a predetermined level, minimizes parasitic losses and signal-line distortion, and minimize capacitance variation. The present invention is also operable to reduce the complexity of impedance matching within a high frequency circuit.