Abstract: Micro-emitter arrays and methods of microfabricating such emitter arrays are provided. The microfabricated emitter arrays incorporate a plurality of emitters with heights greater than 280 microns with uniformity of +/?10 microns arranged on a supporting silicon substrate, each emitter comprising an elongated body extending from the top surface of the substrate and incorporating at least one emitter tip on the distal end of the elongated body thereof. The emitters may be disposed on the substrate in an ordered array in an X by Y grid pattern, wherein X and Y can be any number greater than zero. The micro-emitter arrays may utilize a LMIS propellant source including, for example, gallium, indium, bismuth, or tin. The substrate may incorporate at least one through-via providing a fluid pathway for the LMIS propellant to flow from a propellant reservoir beneath the substrate to the top substrate surface whereupon the micro-emitter array is disposed.

Abstract: A silicon alignment pin is used to align successive layer of component made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.

Abstract: Micro-emitter arrays and methods of microfabricating such emitter arrays are provided. The microfabricated emitter arrays incorporate a plurality of emitters with heights greater than 280 microns with uniformity of +/?10 microns arranged on a supporting silicon substrate, each emitter comprising an elongated body extending from the top surface of the substrate and incorporating at least one emitter tip on the distal end of the elongated body thereof. The emitters may be disposed on the substrate in an ordered array in an X by Y grid pattern, wherein X and Y can be any number greater than zero. The micro-emitter arrays may utilize a LMIS propellant source including, for example, gallium, indium, bismuth, or tin. The substrate may incorporate at least one through-via providing a fluid pathway for the LMIS propellant to flow from a propellant reservoir beneath the substrate to the top substrate surface whereupon the micro-emitter array is disposed.

Abstract: A multi-pixel terahertz transceiver is constructed using a stack of semiconductor layers that communicate using vias defined within the semiconductor layers. By using a stack of semiconductor layers, the various electrical functions of each layer can be tested easily without having to assemble the entire transceiver. In addition, the design allows the production of a transceiver having pixels set 10 mm apart.

Abstract: A silicon alignment pin is used to align successive layer of component made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.

Abstract: A silicon alignment pin is used to align successive layers of components made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.

Abstract: A multi-step silicon etching process has been developed to fabricate silicon-based terahertz (THz) waveguide components. This technique provides precise dimensional control across multiple etch depths with batch processing capabilities. Nonlinear and passive components such as mixers and multipliers waveguides, hybrids, OMTs and twists have been fabricated and integrated into a small silicon package. This fabrication technique enables a wafer-stacking architecture to provide ultra-compact multi-pixel receiver front-ends in the THz range.

Abstract: A multi-pixel terahertz transceiver is constructed using a stack of semiconductor layers that communicate using vias defined within the semiconductor layers. By using a stack of semiconductor layers, the various electrical functions of each layer can be tested easily without having to assemble the entire transceiver. In addition, the design allows the production of a transceiver having pixels set 10 mm apart.

Abstract: A multi-step silicon etching process has been developed to fabricate silicon-based terahertz (THz) waveguide components. This technique provides precise dimensional control across multiple etch depths with batch processing capabilities. Nonlinear and passive components such as mixers and multipliers waveguides, hybrids, OMTs and twists have been fabricated and integrated into a small silicon package. This fabrication technique enables a wafer-stacking architecture to provide ultra-compact multi-pixel receiver front-ends in the THz range.

Abstract: A silicon alignment pin is used to align successive layers of components made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.

Abstract: A set of antenna geometries for use in integrated arrays at terahertz frequencies are described. Two fabrication techniques to construct such antennas are presented. The first technique uses an advanced laser micro-fabrication, allowing fabricating advanced 3D geometries. The second technique uses photolithographic processes, allowing the fabrication of arrays on a single wafer in parallel.