Patents by Inventor Cecile Nghiem

Cecile Nghiem has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8051397
    Abstract: Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: November 1, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Thaddeus Clay McCracken, Jong-Chang Lee, Ping-Chih Wu, Cecile Nghiem, Kit Lam Cheong, Patrick John Eichenseer
  • Publication number: 20100122228
    Abstract: Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.
    Type: Application
    Filed: October 12, 2009
    Publication date: May 13, 2010
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Thaddeus Clay MCCRACKEN, Jong-Chang LEE, Ping-Chih WU, Cecile NGHIEM, Kit Lam CHEONG, Patrick John EICHENSEER
  • Patent number: 7603643
    Abstract: Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: October 13, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Thaddeus Clay McCracken, Jong-Chang Lee, Ping-Chih Wu, Cecile Nghiem, Kit Lam Cheong, Patrick John Eichenseer
  • Publication number: 20080184184
    Abstract: Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.
    Type: Application
    Filed: January 30, 2007
    Publication date: July 31, 2008
    Applicant: Cadence Design Systems, Inc.
    Inventors: Thaddeus Clay McCracken, Jong-Chang Lee, Ping-Chih Wu, Cecile Nghiem, Kit Lam Cheong, Patrick John Eichenseer