Abstract: The solution to the shortest path between a source node and multiple destination nodes is accelerated using a grouping of nodes, where the nodes are grouped based on distance from the source node, and a corresponding set of memory locations that indicate when a group includes one or more nodes. The memory locations can be quickly searched to determine the group that represents the shortest distance from the source node and that includes one or more nodes. Nodes may be grouped into additional groupings that do not correspond to the set of memory locations, when the distance from the source node to the nodes exceeds the range of memory locations. Advantageously, the disclosed system and method provide the ability to reach asymptotically optimal performance.

Abstract: An integrated circuit has a hardware decoder that parses a frame to identify a type of encapsulation. The integrated circuit also has a number of hardware parsers, each parser being coupled to the decoder by an enable line. During packet processing, one of the parsers is enabled by the decoder, based on the value which identifies the encapsulation type. The enabled parser retrieves one or more attributes from the frame, depending on the encapsulation. The integrated circuit also has a register, coupled to each parser. The register holds the attributes retrieved by the parser. The integrated circuit also has a key generation hardware which creates a key, by concatenating from the attributes register, certain attributes that are pre-selected by a user for forming the key. The integrated circuit supplies the key to a memory to look up a set of user-specified actions to be performed on data in the frame.

Abstract: An integrated circuit has a hardware decoder that parses a frame to identify a type of encapsulation. The integrated circuit also has a number of hardware parsers, each parser being coupled to the decoder by an enable line. During packet processing, one of the parsers is enabled by the decoder, based on the value which identifies the encapsulation type. The enabled parser retrieves one or more attributes from the frame, depending on the encapsulation. The integrated circuit also has a register, coupled to each parser. The register holds the attributes retrieved by the parser. The integrated circuit also has a key generation hardware which creates a key, by concatenating from the attributes register, certain attributes that are pre-selected by a user for forming the key. The integrated circuit supplies the key to a memory to look up a set of user-specified actions to be performed on data in the frame.

Abstract: The solution to the shortest path between a source node and multiple destination nodes is accelerated using a grouping of nodes, where the nodes are grouped based on distance from the source node, and a corresponding set of memory locations that indicate when a group includes one or more nodes. The memory locations can be quickly searched to determine the group that represents the shortest distance from the source node and that includes one or more nodes. Nodes may be grouped into additional groupings that do not correspond to the set of memory locations, when the distance from the source node to the nodes exceeds the range of memory locations. Advantageously, the disclosed system and method provide the ability to reach asymptotically optimal performance.

Abstract: The solution to the shortest path between a source node and multiple destination nodes is accelerated using a grouping of nodes, where the nodes are grouped based on distance from the source node, and a corresponding set of memory locations that indicate when a group includes one or more nodes. The memory locations can be quickly searched to determine the group that represents the shortest distance from the source node and that includes one or more nodes. Nodes may be grouped into additional groupings that do not correspond to the set of memory locations, when the distance from the source node to the nodes exceeds the range of memory locations. Advantageously, the disclosed system and method provide the ability to reach asymptotically optimal performance.

Abstract: An integrated circuit has a hardware decoder that parses a frame to identify a type of encapsulation, such as Ethernet v2 encapsulation or 802.3 with or without one or more VLAN tags. The integrated circuit also has a number of hardware parsers, each parser being coupled to the decoder by an enable line. During packet processing, one of the parsers is enabled by the decoder, based on the value which identifies the encapsulation type. The enabled parser retrieves one or more attributes from the frame, depending on the encapsulation. The integrated circuit also has a register, coupled to each parser. The register holds the attributes retrieved by the parser. The integrated circuit also has a key generation hardware which creates a key, by concatenating from the attributes register, certain attributes that are pre-selected by a user for forming the key. The integrated circuit supplies the key to a memory (which may be either in the integrated circuit i.e. on-chip or outside the integrated circuit i.e.

Abstract: An integrated circuit has a hardware decoder that parses a frame to identify a type of encapsulation. The integrated circuit also has a number of hardware parsers, each parser being coupled to the decoder by an enable line. During packet processing, one of the parsers is enabled by the decoder, based on the value which identifies the encapsulation type. The enabled parser retrieves one or more attributes from the frame, depending on the encapsulation. The integrated circuit also has a register, coupled to each parser, to hold the attributes. The integrated circuit also has a key generation hardware which creates a key, by concatenating from the attributes register, certain attributes that are pre-selected by a user for forming the key. The integrated circuit uses the key to look up in memory a set of user-specified actions that are then performed on data in the frame.

Abstract: The solution to the shortest path between a source node and multiple destination nodes is accelerated using a grouping of nodes, where the nodes are grouped based on distance from the source node, and a corresponding set of memory locations that indicate when a group includes one or more nodes. The memory locations can be quickly searched to determine the group that represents the shortest distance from the source node and that includes one or more nodes. Nodes may be grouped into additional groupings that do not correspond to the set of memory locations, when the distance from the source node to the nodes exceeds the range of memory locations. Advantageously, the disclosed system and method provide the ability to reach asymptotically optimal performance.

Abstract: Methods and systems for providing redundant network connectivity across a network using a tunneling protocol by dynamically moving a TLS tunnel between master and slave switches based on relative connectivity provided by the switches are disclosed. A standby routing protocol executes on the master and slave switches to monitor the relative connectivity. In response to detecting that the relative connectivity of the slave switch exceeds that of the master switch, the standby routing protocol reverses the roles of the master and slave switches, thus moving the TLS tunnel to the new master switch.

Abstract: Methods and systems for efficiently delivering data to multiple destinations in a computer network are disclosed. Data to be delivered to multiple destinations is stored in memory. The stored data is divided into blocks. Checksums are pre-calculated for each block. Pre-calculated checksums are used to calculate the data checksums for data to be inserted in each packet to be delivered to data destinations.