Abstract: The present disclosure relates to an interface comprising: a terminal for delivering a DC voltage; a comparator for delivering a first signal representative of a comparison of the DC voltage with a high threshold; a comparator for delivering a second signal representative of a comparison of the DC voltage with a low threshold; and a circuit configured to: deliver successive pairs of values of high and low thresholds for a time period after the DC voltage crosses a first value of the low threshold; modify successive pairs of values of the thresholds based on the first and second signals to determine values of thresholds surrounding the DC voltage; and determining a current value of the DC voltage based on the values of thresholds surrounding the DC voltage.

Abstract: The present disclosure relates to an interface comprising: a terminal for delivering a DC voltage; a comparator for delivering a first signal representative of a comparison of the DC voltage with a high threshold; a comparator for delivering a second signal representative of a comparison of the DC voltage with a low threshold; and a circuit configured to: deliver successive pairs of values of high and low thresholds for a time period after the DC voltage crosses a first value of the low threshold; modify successive pairs of values of the thresholds based on the first and second signals to determine values of thresholds surrounding the DC voltage; and determining a current value of the DC voltage based on the values of thresholds surrounding the DC voltage.

Abstract: A power supply generates a power supply signal to provide electric power over a USB type-C bus. The power supply includes temperature sensing circuitry which senses indications of temperature of the power supply. Control circuitry coupled to the power supply circuitry and the temperature sensing circuitry compares indications of temperature sensed by the temperature sensing circuitry to three thresholds. The control circuitry determines a limit on available electric power provided by the power supply circuitry over the USB type-C bus based on the comparing. The limit on available electric power is set to one of three or more power levels based on the comparing.

Abstract: A device is for detecting a relative positioning of two clock signals including a fast clock signal and a slow clock signal. The fast clock frequency may be n times greater than a slow clock frequency, and n includes an integer greater than 1. The device includes a phase logic signal generator for generating a phase logic signal from the two clock signals by assigning a predetermined logic value to the phase logic signal when a rising edge of the fast clock signal matches a predetermined location of the slow clock signal.

Abstract: A device is for detecting a relative positioning of two clock signals including a fast clock signal and a slow clock signal. The fast clock frequency may be n times greater than a slow clock frequency, and n includes an integer greater than 1. The device includes a phase logic signal generator for generating a phase logic signal from the two clock signals by assigning a predetermined logic value to the phase logic signal when a rising edge of the fast clock signal matches a predetermined location of the slow clock signal.