Patents by Inventor Cedric Koch-Hofer

Cedric Koch-Hofer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Network chip design for grid communication
    Patent number: 7716393
    Abstract: A system includes a plurality of integrated circuits for propagating data between at least one central processing unit and another component of the system. The plurality of integrated circuits are configured for proximity I/O communication. The plurality of integrated circuits is configured such that data propagation through the plurality of integrated circuits is unaffected by a rotation of at least one of the plurality of integrated circuits by 90 degrees.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: May 11, 2010
    Assignee: Oracle America, Inc.
    Inventors: Xavier-Francois Vigouroux, Bernard Tourancheau, Cedric Koch-Hofer
  • Optimal communication path routing in a system employing interconnected integrated circuit technology
    Patent number: 7656805
    Abstract: An electronic system in which integrated circuits employing cornered I/O are arranged in a framework including an optional path manager and at least one updateable routing table. Packet routing options are described with solutions being provided to minimize transmission latency and pathway alternatives.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: February 2, 2010
    Assignee: Sun Microsystems, Inc.
    Inventors: Xavier-Francois Vigouroux, Bernard Tourancheau, Cedric Koch-Hofer
  • System and method for determining a carrier layout using cornered chip-to-chip input/output
    Patent number: 7191422
    Abstract: A system and method for determining a carrier layout using cornered chip-to-chip input/output is presented. Each of a plurality of individual integrated circuit carriers communicatively interfaceable through cornered input/output ports is oriented at a uniform rotation relative to an edge of a carrier layout. Each carrier defines a set of rectilinear edges. Each carrier is placed juxtaposed at an open corner to at least one other carrier within a rectilinear lattice topologically arranged in the carrier layout to substantially minimize Hamming distances between each of the carriers.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: March 13, 2007
    Assignee: Sun Microsystems, Inc.
    Inventors: Bernard Tourancheau, Xavier-Francois Vigouroux, Cedric Koch-Hofer
  • Network chip design for grid communication
    Publication number: 20060224796
    Abstract: A system includes a plurality of integrated circuits for propagating data between at least one central processing unit and another component of the system. The plurality of integrated circuits are configured for proximity I/O communication. The plurality of integrated circuits is configured such that data propagation through the plurality of integrated circuits is unaffected by a rotation of at least one of the plurality of integrated circuits by 90 degrees.
    Type: Application
    Filed: June 9, 2005
    Publication date: October 5, 2006
    Applicant: Sun Microsystems, Inc.
    Inventors: Xavier-Francois Vigouroux, Bernard Tourancheau, Cedric Koch-Hofer
  • Optimal communication path routing in a system employing interconnected integrated circuit technology
    Publication number: 20060018261
    Abstract: An electronic system is described in which integrated circuits employing cornered I/O are arranged in a framework including an optional path manager and at least one updateable routing table. Packet routing options are described with solutions being provided to minimize transmission latency and pathway alternatives.
    Type: Application
    Filed: September 2, 2005
    Publication date: January 26, 2006
    Applicant: Sun Microsystems, Inc.
    Inventors: Xavier-Francois Vigouroux, Bernard Tourancheau, Cedric Koch-Hofer