Patents by Inventor Cedric Maufront

Cedric Maufront has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8266494
    Abstract: A data bus including a plurality of logic blocks coupled in series, each logic block including at least one buffer for buffering at least one data bit transmitted via the data bus and at least one of the logic blocks further including circuitry coupled in parallel with the at least one buffer and arranged to determine a first bit of error correction code associated with the at least one data bit.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: September 11, 2012
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Richard Ferrant, Cédric Maufront
  • Publication number: 20090125789
    Abstract: A data bus including a plurality of logic blocks coupled in series, each logic block including at least one buffer for buffering at least one data bit transmitted via the data bus and at least one of the logic blocks further including circuitry coupled in parallel with the at least one buffer and arranged to determine a first bit of error correction code associated with the at least one data bit.
    Type: Application
    Filed: June 17, 2008
    Publication date: May 14, 2009
    Applicant: STMicroelectronics Crolles 2 SAS
    Inventors: Richard Ferrant, Cedric Maufront
  • Patent number: 7298643
    Abstract: A magnetoresistive memory element including a trapped magnetic region and a free magnetic region separated by a barrier layer. The free magnetic region comprises a stacking of at least two antiferromagnetically-coupled ferromagnetic layers, a layer magnetic moment vector being associated with each layer, the resulting magnetic moment vector, equal to the sum of the layer magnetic moment vectors, having an amplitude smaller than at least 40% of the amplitude of the layer magnetic moment vector of maximum amplitude. The anisotropy field and/or the demagnetizing field tensor is not identical for the at least two ferromagnetic layers, whereby the angular deviations of the layer magnetic moment vectors are different at the time of the application of an external magnetic field, which enables at least two methods for directly writing into the memory element, as well as its initialization.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: November 20, 2007
    Assignees: STMicroelectronics SA, Centre National de la Recherche Scientifique, Universite de Paris SUD (Paris XI)
    Inventors: Joo-Von Kim, Thibaut Devolder, Claude Chappert, Cedric Maufront, Richard Fournel
  • Publication number: 20050237796
    Abstract: A magnetoresistive memory element including a trapped magnetic region and a free magnetic region separated by a barrier layer. The free magnetic region comprises a stacking of at least two antiferromagnetically-coupled ferromagnetic layers, a layer magnetic moment vector being associated with each layer, the resulting magnetic moment vector, equal to the sum of the layer magnetic moment vectors, having an amplitude smaller than at least 40% of the amplitude of the layer magnetic moment vector of maximum amplitude. The anisotropy field and/or the demagnetizing field tensor is not identical for the at least two ferromagnetic layers, whereby the angular deviations of the layer magnetic moment vectors are different at the time of the application of an external magnetic field, which enables at least two methods for directly writing into the memory element, as well as its initialization.
    Type: Application
    Filed: April 25, 2005
    Publication date: October 27, 2005
    Applicants: STMicroelectronics S.A., Centre National de la Recherche Scientifique, Universite de Paris Sud (Paris XI)
    Inventors: Joo-Von Kim, Thibaut Devolder, Claude Chappert, Cedric Maufront, Richard Fournel