Patents by Inventor Cedric Rechatin

Cedric Rechatin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • AMPLIFIER FOR A RADIO FREQUENCY RECEIVER
    Publication number: 20230018356
    Abstract: In an embodiment an amplifier includes a first MOS transistor having a drain connected to an output of the amplifier and a source coupled to a first node configured to receive a first power supply potential, a first capacitive element connected between an input of the amplifier and a gate of the first MOS transistor, a first current source connecting the drain of the first MOS transistor to a second node configured to receive a second power supply potential and a resistive element and a second capacitive element connected in parallel between the gate and the drain of the first MOS transistor, the resistive element including a switched capacitor.
    Type: Application
    Filed: July 12, 2022
    Publication date: January 19, 2023
    Inventors: Hugo Gicquel, Sandrine Nicolas, Cedric Rechatin, Reiner Welk
  • Biasing current regularization loop stabilization
    Patent number: 10359800
    Abstract: An integrated circuit includes a first stage configured to receive a bias current. A current regulation loop includes a transimpedance amplifier having a first transistor, and a second transistor having a gate coupled to a gate of the first transistor. The first transistor and the second transistor are configured to compare the bias current with a reference current, and to generate a regulation voltage on an output node of the transimpedance amplifier. A capacitor is coupled between the output node of the transimpedance amplifier and the gates of the first and second transistors.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 23, 2019
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SAS
    Inventors: Serge Ramet, Sandrine Nicolas, Danika Perrin, Cedric Rechatin
  • BIASING CURRENT REGULARIZATION LOOP STABILIZATION
    Publication number: 20180239384
    Abstract: An integrated circuit includes a first stage configured to receive a bias current. A current regulation loop includes a transimpedance amplifier having a first transistor, and a second transistor having a gate coupled to a gate of the first transistor. The first transistor and the second transistor are configured to compare the bias current with a reference current, and to generate a regulation voltage on an output node of the transimpedance amplifier. A capacitor is coupled between the output node of the transimpedance amplifier and the gates of the first and second transistors.
    Type: Application
    Filed: August 31, 2017
    Publication date: August 23, 2018
    Inventors: Serge Ramet, Sandrine Nicolas, Danika Perrin, Cedric Rechatin