Patents by Inventor Cedric Speltz

Cedric Speltz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PRESSING SOLDER BUMPS TO MATCH PROBE PROFILE DURING WAFER LEVEL TESTING
    Publication number: 20180358321
    Abstract: A method of pressing solder bumps using a pressing apparatus before testing a wafer, including loading the wafer into the pressing apparatus, where the wafer includes a number of chips, and the wafer is aligned with respect to a test head of the pressing apparatus. The test head includes a substrate which has pressing structures arranged across a surface of the substrate facing the wafer. The pressing structures contact the solder bumps, where the solder bumps include a first surface topology and the pressing structures include a pressing surface topology prior to the contact. The caused contact includes altering a shape of each of the plurality of solder bumps, such that the plurality of solder bumps then a second surface topology after the caused contact, and the second surface topology of the solder bumps matches the pressing surface topology after the caused contact.
    Type: Application
    Filed: June 13, 2017
    Publication date: December 13, 2018
    Inventors: David M. Audette, Sukjay Chey, Dennis R. Conti, Marc D. Knox, Sankeerth Rajalingam, Cedric Speltz, Grant Wagner
  • PRESSING SOLDER BUMPS TO MATCH PROBE PROFILE DURING WAFER LEVEL TESTING
    Publication number: 20180358322
    Abstract: A method of pressing solder bumps using a pressing apparatus before testing a wafer, including loading the wafer into the pressing apparatus, where the wafer includes a number of chips, and the wafer is aligned with respect to a test head of the pressing apparatus. The test head includes a substrate which has pressing structures arranged across a surface of the substrate facing the wafer. The pressing structures contact the solder bumps, where the solder bumps include a first surface topology and the pressing structures include a pressing surface topology prior to the contact. The caused contact includes altering a shape of each of the plurality of solder bumps, such that the plurality of solder bumps then a second surface topology after the caused contact, and the second surface topology of the solder bumps matches the pressing surface topology after the caused contact.
    Type: Application
    Filed: December 19, 2017
    Publication date: December 13, 2018
    Inventors: David M. Audette, Sukjay Chey, Dennis R. Conti, Marc D. Knox, Sankeerth Rajalingam, Cedric Speltz, Grant Wagner
  • PRESSING SOLDER BUMPS TO MATCH PROBE PROFILE DURING WAFER LEVEL TESTING
    Publication number: 20180358323
    Abstract: A method of pressing solder bumps using a pressing apparatus before testing a wafer, including loading the wafer into the pressing apparatus, where the wafer includes a number of chips, and the wafer is aligned with respect to a test head of the pressing apparatus. The test head includes a substrate which has pressing structures arranged across a surface of the substrate facing the wafer. The pressing structures contact the solder bumps, where the solder bumps include a first surface topology and the pressing structures include a pressing surface topology prior to the contact. The caused contact includes altering a shape of each of the plurality of solder bumps, such that the plurality of solder bumps then a second surface topology after the caused contact, and the second surface topology of the solder bumps matches the pressing surface topology after the caused contact.
    Type: Application
    Filed: December 21, 2017
    Publication date: December 13, 2018
    Inventors: David M. Audette, Sukjay Chey, Dennis R. Conti, Marc D. Knox, Sankeerth Rajalingam, Cedric Speltz, Grant Wagner