Abstract: An integrated circuit having an on-chip access right manager to grant or deny access to a memory segment to a peripheral device such as a CPU (Central Processing Unit), DSP (Digital Signal Processor) or DMA (Direct Memory Access) unit according to predetermined access rights upon reception of a read instruction from the peripheral device, and an on-chip lock connected to a memory data bus, the lock being controllable by the access right manager to block access to a logical one or zero set on each memory data bus wires as long as the access to the memory segment is not granted. Upon reception of the read instruction from the peripheral device, the integrated circuit is configured to start both the process of setting, by the on chip memory, of either a logical one or a logical zero on each of the wires of the memo data bus, as well as the process of granting or refusing the access to the memory segment by the on-chip access right manager to the peripheral device.

Abstract: The integrated circuit comprises: —an on-chip access right manager (40) to grant or deny access to a memory segment to a peripheral device (10) according to predetermined access rights upon reception of a read instruction from the peripheral device, —an on-chip lock (50) connected to a memory data bus, the lock being controllable by the access tight manager to block access to a logical one or zero set on each memory data bus wires as long as the access to the memory segment is not granted.