Abstract: Embodiments of this application provide a semiconductor device, an electronic device, and a semiconductor device preparation method, and relate to the field of chip manufacturing and packaging technologies, to improve heat dissipation efficiency of the semiconductor device without increasing a size. The semiconductor device includes: a substrate, a source, a drain, a gate, and a groove. The source, the drain, and the gate are all formed on the substrate, and an active region is formed between the source and the drain on the substrate. The groove is disposed in the substrate, and a spacing is formed between the groove and the active region. A heat dissipation layer is formed in the groove, and a coefficient of thermal conductivity of the heat dissipation layer is greater than that of the substrate.

Abstract: The technology of this application relates to a high electron mobility transistor including a GaN substrate layer, a barrier layer, a circuit layer, and a field plate that are sequentially stacked. The GaN substrate layer includes a main body layer and a channel layer that are stacked, the channel layer is adjacent to the barrier layer, the circuit layer includes a source, a drain, and a dielectric layer, the dielectric layer is disposed between the source and the drain, the field plate is disposed on a side that is of the dielectric layer and that is away from the barrier layer, an orthographic projection of the field plate on the channel layer is a field plate projection, the channel layer includes a modulation region and a non-modulation region, the non-modulation region surrounds the modulation region, the modulation region and the field plate projection at least partially overlap.

Abstract: A semiconductor device includes a substrate, a gate, a second dielectric layer, and a field plate. The substrate has a first dielectric layer, and a thickness of the first dielectric layer in a first area is greater than a thickness of the first dielectric layer in a second area outside the first area. The gate is located on the substrate and in the first area, the gate includes a first gate structure and a second gate structure, and the second gate structure is formed on a side of the first dielectric layer that is away from the substrate and covers a part of the first dielectric layer. The second dielectric layer covers the gate and the first dielectric layer. The field plate is located on the second dielectric layer and is disposed in both the first area and the second area.