Abstract: Applications for physical layer security are disclosed. One such application is a system comprising a medical sensor device and a wireless communication module. The medical sensor device is operable to generate data representative of a condition of a patient. The wireless communication module is operable to transmit, on a wireless communication channel, the generated data representative of the condition of the patient. The system also includes a physical layer security module residing at a physical layer of the wireless communication module. The physical layer security module is operable to provide a secrecy zone around the physical layer security module by transforming the generated data such that transmission of the generated data is secured from interception by an eavesdropper on the wireless communication channel.

Abstract: Systems, devices, and methods of physical layer security are disclosed. One such device includes a physical layer security module and a physical layer processing module. The physical layer security module is operable to transform user data in accordance with security characteristics. The physical layer processing module is operable to process the transformed data into a format suitable for the communication channel and further operable to transmit the processed data onto the communication channel. The security characteristics of the physical layer security module are such that decoding the intercepted user data by the eavesdropper results in a bit error rate of about one-half.

Abstract: Systems and methods of secure data exchange are disclosed. One such method includes obtaining user data at a physical layer of a transmitter and securing the user data at the physical layer. The user data is secured by processing the user data with a series of non-recursive convolutional encoders interspersed with one or more bit-level permuters. The secured user data is transmitted.

Abstract: A system includes an error correction encoder that encodes data and produces parity bits, and a parity bit processor that disperses the parity bits across the data, placing respective i-bit parity sub-blocks between selected multiple-bit data sub-blocks. The system also modifies one or more of the bits in predetermined positions in respective data sub-blocks based on the bits of the parity sub-blocks that precede them, such that the precoding does not sign invert the data sub-blocks.

Abstract: The present invention describes systems and methods for providing physical layer security. An exemplary embodiment of the present invention provides a method of providing physical layer security involving receiving message data at a pre-processing device in a wireless transmission device. Furthermore, the method of providing physical layer security involves pre-processing the message data into channel data with the pre-processing device and transmitting the channel data from the wireless transmission device over a wireless transmission link having a path loss. Subsequently, the method of providing physical layer security involves receiving the channel data at a post-processing module in a reception device. Additionally, the method involves post-processing the channel data into the message data with the post-processing module, such that an unauthorized reception device is unable to post-process the channel data when a path loss experienced over the transmission link is greater than a predetermined value.

Abstract: A system includes an encoder that manipulates postcoded data and produces parity bits, and a parity bit encoder that produces encoded parity bits by inserting into the parity bits one or more flags with polarities, or states, that are selected to produce, after precoding, precoded parity bits that meet predetermined modulation constraints.

Abstract: A communication channel including Reed-Solomon (RS) and single-parity-check (SPC) encoding/decoding. Multiple RS codewords are combined and then SPC encoded into an RS/SPC array. A soft-input soft-output (SISO) channel detector detects the RS/SPC encoded bits and provides soft (reliability) information on these bits. A combined RS and SPC error correction block provides a recovered user output. An iterative soft input decoding algorithm combines RS and SPC error correction.

Abstract: An interleaver has an input multiplexer that receives a data sequence at an interleaver input and that separates the data sequence into multiple data sub-blocks. The interleaver has a linear feedback shift register that generates an input address sequence. The interleaver has adder circuits that generate output address sequences associated with each data sub-block. The interleaver has memory that stores the data sub-blocks at addresses controlled by the input address sequence. The memory reproduces each data sub-block in an interleaved sequence controlled by the associated output address sequence. The interleaver has an output multiplexer that assembles the interleaved sequences to provide an interleaver output.

Abstract: A system includes a precoder-aware running digital sum (RDS) encoder that encodes user data as w-bit sub-blocks, to produce an encoded data block that meets block RDS constraints and consists of encoded data sub-blocks that meet sub-block RDS constraints. The sub-block constraints include the data sub-blocks having the same magnitude RDS before and after precoding. The encoder data block is further encoded using an error correction code to produce parity bits, and the parity bits are dispersed, as i-bit parity sub-blocks, between selected data sub-blocks to form a code word. The code word is then precoded to produce a precoded bit sequence for transmission over a channel. Sub-block run length limit (“RLL”) constraints may also be included, such that the encoded data block meets both RLL and RDS, with the encoded data sub-blocks meeting respective RLL and RDS sub-block constraints.

Abstract: A system includes a precoder-aware running digital sum (RDS) encoder that encodes user data as w-bit sub-blocks, to produce an encoded data block that meets block RDS constraints and consists of encoded data sub-blocks that meet sub-block RDS constraints. The sub-block constraints include the data sub-blocks having the same magnitude RDS before and after precoding. The encoder data block is further encoded using an error correction code to produce parity bits, and the parity bits are dispersed, as i-bit parity sub-blocks, between selected data sub-blocks to form a code word. The code word is then precoded to produce a precoded bit sequence for transmission over a channel. Sub-block run length limit (“RLL”) constraints may also be included, such that the encoded data block meets both RLL and RDS, with the encoded data sub-blocks meeting respective RLL and RDS sub-block constraints.

Abstract: A system includes an error correction encoder that encodes data and produces parity bits, and a parity bit processor that disperses the parity bits across the data, placing respective i-bit parity sub-blocks between selected multiple-bit data sub-blocks. The system also modifies one or more of the bits in predetermined positions in respective data sub-blocks based on the bits of the parity sub-blocks that precede them, such that the precoding does not sign invert the data sub-blocks.

Abstract: A system includes an encoder that manipulates postcoded data and produces parity bits, and a parity bit encoder that produces encoded parity bits by inserting into the parity bits one or more flags with polarities, or states, that are selected to produce, after precoding, precoded parity bits that meet predetermined modulation constraints.

Abstract: An interleaver has an input multiplexer that receives a data sequence at an interleaver input and that separates the data sequence into multiple data sub-blocks. The interleaver has a linear feedback shift register that generates an input address sequence. The interleaver has adder circuits that generate output address sequences associated with each data sub-block. The interleaver has memory that stores the data sub-blocks at addresses controlled by the input address sequence. The memory reproduces each data sub-block in an interleaved sequence controlled by the associated output address sequence. The interleaver has an output multiplexer that assembles the interleaved sequences to provide an interleaver output.

Abstract: A data communication system has a combiner circuit that combines a set of information symbols with error correction codes and that generates a set of product codes that are at least three dimensional. A communication channel receives the set of product codes and provides the set of product codes with errors after a channel delay. A channel detector receives the set of product codes with the errors and generates a channel detector output. An error correction circuit receives the channel detector output and iteratively removes the errors to provide a set of reproduced information symbols with a reduced number of the errors.

Abstract: An interleaver has an input multiplexer that receives a data sequence at an interleaver input and that separates the data sequence into multiple data sub-blocks. The interleaver has a linear feedback shift register that generates an input address sequence. The interleaver has adder circuits that generate output address sequences associated with each data sub-block. The interleaver has memory that stores the data sub-blocks at addresses controlled by the input address sequence. The memory reproduces each data sub-block in an interleaved sequence controlled by the associated output address sequence. The interleaver has an output multiplexer that assembles the interleaved sequences to provide an interleaver output.

Abstract: A communication channel including Reed-Solomon (RS) and single-parity-check (SPC) encoding/decoding. Multiple RS codewords are combined and then SPC encoded into an RS/SPC array. A soft-input soft-output (SISO) channel detector detects the RS/SPC encoded bits and provides soft (reliability) information on these bits. A combined RS and SPC error correction block provides a recovered user output. An iterative soft input decoding algorithm combines RS and SPC error correction.

Abstract: A communication system includes an encoder that receives user data and includes running digital sum encoding and turbo encoding. The running digital sum encoding is preserved in an encoder output to a channel. A decoder receives a channel output and comprises running digital sum decoding and turbo decoding to reproduce the user data in a decoder output.

Abstract: An interleaver has an input multiplexer that receives a data sequence at an interleaver input and that separates the data sequence into multiple data sub-blocks. The interleaver has a linear feedback shift register that generates an input address sequence. The interleaver has adder circuits that generate output address sequences associated with each data sub-block. The interleaver has memory that stores the data sub-blocks at addresses controlled by the input address sequence. The memory reproduces each data sub-block in an interleaved sequence controlled by the associated output address sequence. The interleaver has an output multiplexer that assembles the interleaved sequences to provide an interleaver output.

Abstract: A communication system includes an encoder that receives user data and includes running digital sum encoding and turbo encoding. The running digital sum encoding is preserved in an encoder output to a channel. A decoder receives a channel output and comprises running digital sum decoding and turbo decoding to reproduce the user data in a decoder output.

Abstract: A data communication system has a combiner circuit that combines a set of information symbols with error correction codes and that generates a set of product codes that are at least three dimensional. A communication channel receives the set of product codes and provides the set of product codes with errors after a channel delay. A channel detector receives the set of product codes with the errors and generates a channel detector output. An error correction circuit receives the channel detector output and iteratively removes the errors to provide a set of reproduced information symbols with a reduced number of the errors.