Abstract: A fluid sensor for sensing a concentration or composition of a fluid, the sensor comprising a first temperature sensing element located on or within a first dielectric membrane and a second temperature sensing element located on or within a second dielectric membrane. An output circuit is configured to measure a differential signal between the first temperature sensing element and the second temperature sensing element. The fluid sensor comprises a first region configured to be exposed to the fluid, and a second region configured to be isolated from the fluid, where the first dielectric membrane is located in the first region, such that in use, the first dielectric membrane is exposed to the fluid, and wherein the second dielectric membrane is located in the second region such that in use, the second dielectric membrane is isolated from the fluid.

Abstract: We disclose herein a flow sensor comprising: a first substrate comprising an etched portion, a dielectric region located on a first side of the first substrate, wherein the dielectric region comprises at least one dielectric membrane located over the etched portion of the first substrate, a sensing element located on or within the dielectric membrane, and a second substrate adjoining a second side of the first substrate. The first side of the first substrate and the second side of the first substrate are opposite sides. The first substrate and the second substrate cooperate to form a sensing channel through the flow sensor.

Abstract: A flow sensor assembly comprising a first substrate, a flow sensor located over the first substrate, a lid located over the first substrate and the flow sensor, a flow inlet channel, a flow outlet channel, and an overmold laterally encircling the flow sensor. The overmold is in contact with the side walls of the flow sensor, and extends between the flow sensor and the lid such that the overmold, the flow sensor, and the lid define a flow sensing channel between the flow inlet channel and the flow outlet channel. the lid and the encapsulation cooperate to define the flow inlet channel and the flow outlet channel.

Abstract: We disclose herein a flow sensor assembly comprising a first substrate, a flow sensor located over the first substrate, a lid located over the flow sensor, a flow inlet channel, and a flow outlet channel. A surface of the flow sensor and a surface of the lid cooperate to form a flow sensing channel between the flow inlet channel and the flow outlet channel, and a surface of the flow sensing channel is substantially flat throughout the length of the flow sensing channel.

Abstract: We disclose herein a flow sensor comprising: a first substrate comprising an etched portion, a dielectric region located on a first side of the first substrate, wherein the dielectric region comprises at least one dielectric membrane located over the etched portion of the first substrate, a sensing element located on or within the dielectric membrane, and a second substrate adjoining a second side of the first substrate. The first side of the first substrate and the second side of the first substrate are opposite sides. The first substrate and the second substrate cooperate to form a sensing channel through the flow sensor.

Abstract: We disclose herein a flow sensor assembly comprising a first substrate, a flow sensor located over the first substrate, a lid located over the flow sensor, a flow inlet channel, and a flow outlet channel. A surface of the flow sensor and a surface of the lid cooperate to form a flow sensing channel between the flow inlet channel and the flow outlet channel, and a surface of the flow sensing channel is substantially flat throughout the length of the flow sensing channel.

Abstract: A high voltage/power semiconductor device has a semiconductor layer having a high voltage terminal end and a low voltage terminal end. A drift region extends between the high and low voltage terminal ends. A dielectric layer is provided above the drift region. An electrical conductor extends across at least a part of the dielectric layer above the drift region, the electrical conductor being connected or connectable to the high voltage terminal end. The drift region has plural trenches positioned below the electrical conductor. The trenches extend laterally across at least a part of the drift region in the direction transverse the direction between the high and low voltage terminal ends of the semiconductor layer, each trench containing a dielectric material. The trenches improve the distribution of electric field in the device in the presence of the electrical conductor.

Abstract: A high voltage/power semiconductor device has a semiconductor layer having a high voltage terminal end and a low voltage terminal end. A drift region extends between the high and low voltage terminal ends. A dielectric layer is provided above the drift region. An electrical conductor extends across at least a part of the dielectric layer above the drift region, the electrical conductor being connected or connectable to the high voltage terminal end. The drift region has plural trenches positioned below the electrical conductor. The trenches extend laterally across at least a part of the drift region in the direction transverse the direction between the high and low voltage terminal ends of the semiconductor layer, each trench containing a dielectric material. The trenches improve the distribution of electric field in the device in the presence of the electrical conductor.

Abstract: A new method of forming liquid crystal displays has been achieved. Metal conductors are provided in an insulating layer overlying a semiconductor substrate. A first isolation layer is deposited. A first silicon nitride layer is deposited. The first silicon nitride layer is patterned to form openings for planned vias overlying the metal conductors. A second isolation layer is deposited. A second silicon nitride layer is deposited. The second silicon nitride layer is patterned to form masks overlying where dummy supports for the metal pixels are planned and to form openings to extend the planned vias. A third isolation layer is deposited. The third isolation layer is patterned to form openings for the planned metal pixels. The second isolation layer and the first isolation layer are etched through to complete the vias and the dummy supports. A metal layer is deposited filling the openings for the metal pixels, the dummy support, and the vias.

Abstract: A new method is provided for the creation of a resistive load in a semiconductor device whereby the semiconductor device further contains gate electrodes and a capacitor. Field isolation regions separate the active areas; a thin layer of gate oxide is created over these active regions. A first layer of poly is deposited, used for the gate electrode, for the bottom plate of the adjacent capacitor and for the resistor of high ohmic value. The gate poly is doped (in the first layer of poly); optionally the bottom plate of the capacitor can be doped. A dielectric layer is deposited for the dielectric of the capacitor; a second layer of poly is deposited, patterned and etched to form the capacitor top plate. The capacitor (dielectric and bottom plate), poly gates and the load resistor are patterned; the LDD regions for the transistors are created.

Abstract: A method of fabricating an anti-fuse module and dual damascene interconnect structure comprises the following steps. A semiconductor structure having at least two exposed metal lines covered by a first dielectric layer is provided. A first metal line is within an anti-fuse area and a second metal line is within an interconnect area. A first metal via is formed within the first dielectric layer within the anti-fuse area with the first metal via contacting the first metal line. A SiN layer is deposited over the first dielectric layer and the first metal via. The SiN layer is patterned to form at least two openings. A first opening exposes the first metal via, and a second opening exposes a portion of the first dielectric layer above the second metal line. A fusing element layer is deposited and patterned over the patterned SiN layered structure to form a fusing element over the first metal via.

Abstract: A method for fabricating a metal-oxide-metal capacitor using a dual damascene process is described. A dielectric layer is provided overlying a semiconductor substrate. A dual damascene opening in the dielectric layer is filled with copper to form a copper via underlying a copper line. A first metal layer is deposited overlying the copper line and patterned to form a bottom capacitor plate contacting the copper line. A capacitor dielectric layer is deposited overlying the bottom capacitor plate. A second metal layer is deposited overlying the capacitor dielectric layer and patterned to form a top capacitor plate to complete fabrication of a metal-oxide-metal capacitor.