Abstract: In controlling data packet transmission for a passive optical network, a controller provides memory access and flow control of packet data from a host memory to an external optical network device, such as an optical line termination, optical network unit, or optical network termination. The controller is programmed to control packet data flow through the transmission buffer by resizing the transmission buffer to compensate for increases or decreases in bandwidth demand. For example, the transmission buffer may include a plurality of FIFOs, each of a different transmission container type and each capable of having a different bandwidth allocation, which allocation is changed by the controller in response any one of the FIFO's usage levels increasing above a high threshold or decreasing below a low threshold.

Abstract: A method of synchronizing with a data transmission in a passive optical network, wherein the data transmission includes a plurality of data transmission frames each having i) a known transmission duration, and ii) a start boundary identified by a predetermined synchronization pattern. The method includes comparing a plurality of data patterns within the data transmission to at least part of a predetermined synchronization pattern; providing a comparison result for each comparison having a match between a data pattern and the at least part of the predetermined synchronization pattern; assigning a frame tracking signal to each one of the plurality of comparison results occurring within the known transmission duration; comparing one or more subsequent data patterns occurring in the data transmission to at least part of the predetermined synchronization pattern for each assigned frame tracking signal; and generating a synchronization signal associated with a selected one of the frame tracking signals.

Abstract: An apparatus including a first memory, a second memory, and a direct memory access engine. The first memory stores one or more packet descriptors. The second memory stores one or more packets for transmission via a communication link. The direct memory access engine is configured to i) determine when the one or more packet descriptors have been written, by a host, to the first memory, ii) read the one or more packet descriptors from the first memory in response to determining that the one or more packet descriptors have been written to the first memory by the host, iii) determine, using the one or more packet descriptors, one or more respective locations of one or more packets in a host memory, and iv) initiate a direct memory access transfer of the one or more packets from the one or more respective locations in the host memory to the second memory.

Abstract: In a method for controlling timing of an upstream from an optical network termination device to an optical line termination device, a downstream transmission is analyzed to determine a core clock rate for the termination device. The core clock signal is then used to determine a transmitter clock signal to be used for upstream transmission, where the transmitter clock signal is offset from the core clock signal. The offset transmitter clock signal may be determined in the receiver or in the transmitter of the termination device and by a delay lock loop or by a clock data recovery/generator circuitry. For example, the transmitter clock signal may be taken from a plurality of phase adjusted clock offset signals created by the clock data recovery/generator circuitry during identification of the core clock signal.

Abstract: In managing and buffering packet data for transmission out of a host, descriptor ring data is pushed in from a host memory into a descriptor ring cache and cached therein. The descriptor ring data is processed to read a data packet descriptor, and a direct memory access is initiated to the host to read the data packet corresponding to the read data packet descriptor to a data transmission buffer. The data packet is written by the direct memory access into the data transmission buffer and cached therein. A return pointer is written to the host memory by the direct memory access indicating that the data packet descriptor has been read and the corresponding data packet has been transmitted. In managing and buffering packet data for transmission to a host, descriptor ring data is pushed in from a host memory into a descriptor ring cache and cached therein. Data packets for transmission to the host memory are received and cached in a data reception buffer.

Abstract: In a method for recovering a data rate of an upstream transmission having rising edge transitions and falling edge transitions, an upstream transmission is coupled into a plurality of register banks, each register bank adapted to oversample the upstream transmission at a different phase offset of a clock signal. An edge transition state is determined for each of the register banks, each edge transition state corresponding to either a rising edge transition or a falling edge transition in the upstream transmission over a clock cycle. The edge transition states of the register banks are analyzed to determine a sampling point of the clock signal for sampling the upstream transmission. The upstream transmission may be transmitted through multiple data rate recovery circuits each operating at a different clock rate, for determining the optimal sampling point and the original data rate of the upstream transmission.

Abstract: A circuit and method to synchronize with a data transmission having a plurality of data transmission frames each with a start boundary identified by a predetermined synchronization pattern, includes comparing sets of data within the data transmission to a predetermined synchronization pattern. A frame tracking signal is assigned to each one of the plurality of comparison results that indicates a match between a data pattern within one of the plurality of sets of data and the predetermined synchronization pattern, including matches that occur multiple times within a known duration of the data transmission frame duration. Based on each frame tracking signal assigned to a comparison result, the start boundary of the data transmission frames is searched. The start boundary may be search by monitoring successive occurrences of the predetermined synchronization pattern in the data transmission at intervals of the known data transmission frame duration for each data matching data pattern.

Abstract: A circuit to synchronize with a data transmission includes a comparator to read a set of data within a serialized data transmission, compare the set of data to a predetermined data pattern and output a comparison result. For a serialized data transmission, the comparator receives the serialized transmission and a shift register serially coupled to the comparator to hold the data pattern. A synchronization detector receives a comparison hit vector based on the comparison result from the comparator and aligns a boundary of a data frame according to the comparison hit vector if the comparison hit vector indicates a match between the data pattern in the set of data and the predetermined data pattern. For a deserialized data transmission, each stage of a multistage shift register read a set of data from the deserialized data transmission and selectively outputs the set of data to a comparator which compares each set to a predetermined data pattern and output a comparison result.

Abstract: In managing and buffering packet data for transmission out of a host, descriptor ring data is pushed in from a host memory into a descriptor ring cache and cached therein. The descriptor ring data is processed to read a data packet descriptor, and a direct memory access is initiated to the host to read the data packet corresponding to the read data packet descriptor to a data transmission buffer. The data packet is written by the direct memory access into the data transmission buffer and cached therein. A return pointer is written to the host memory by the direct memory access indicating that the data packet descriptor has been read and the corresponding data packet has been transmitted. In managing and buffering packet data for transmission to a host, descriptor ring data is pushed in from a host memory into a descriptor ring cache and cached therein. Data packets for transmission to the host memory are received and cached in a data reception buffer.

Abstract: A Network Interface Card (NIC) for integrating computers and other electronic equipment to a Wireless Asynchronous Transfer Mode (WATM) network is constructed so as to efficiently exchange data between a host and the wireless network. In addition to providing both ATM and AAL layer transfer protocols, the NIC also provides Data Link Control (DLC), Media Access Control (MAC), and Radio Physical (RPhy) layers as well.

Abstract: A queue management method for a wireless asynchronous transfer mode Network Interface Card (NIC) for integrating computers and other electronic equipment to a Wireless Asynchronous Transfer Mode (WATM) network is constructed so as to efficiently exchange data between a host and the wireless network. In addition to providing both ATM and AAL layer transfer protocols, the NIC also provides Data Link Control (DLC), Media Access Control (MAC), and Radio Physical (RPhy) layers as well.

Abstract: A method and system are provided for managing memory to reassemble data packets received from different virtual channels in an ATM network. The method and system recognizes that both reliable and best effort traffic must be supported by a network interface. The system makes use of a virtual First-In-First-Out (FIFO) concept that partitions RAM memory space into multiple FIFO queues. The virtual FIFOs can have different sizes, and can be allocated to connections depending on quality of service requirements. A dedicated embedded controller 721 to provide flexibility is used in the system, as well as Content Addressable Memory (CAM) devices 723,724, and external logic. The method and system can also be applied at ATM transmitters in the implementation of congestion control algorithms.

Abstract: Method and system are provided for processing B-ISDN transfer protocols in a telecommunication system utilizing a generic ATM/AAL interface having a programmable electronic circuit. At the ATM Adaptation Layer (AAL), segmentation and reassembly, and convergence sublayer protocols have been developed to support the different service types to be handled. The interface facilitates a cost effective yet relatively simple broadband ATM/AAL terminal adapter that performs ATM and ATM Adaptation Layer processing in a very flexible manner. The terminal adapter handles several different transfer protocols (AAL types 1, 3, 4 and 5) using a single architecture on a per protocol data unit (PDU) basis and may be implemented using field programmable gate arrays and off-the-shelf components. The method and system is flexible enough to support changes in existing, new and future AAL/ATM standards.

Abstract: To recover the service clock of a variable bit rate source (170) which generates data at a rate which is not proportional to a service clock (76), timing cells are generated. The timing cells are generated at a rate which is proportional to the service clock (76). The timing cells and data are transmitted via a network (100). At the receive-end, the data is stored in a buffer (82). A phase locked loop (90') generates a local clock signal in the form of a read signal which controls the rate at which the received data is read out of the buffer (82). The read signal produced by the phase locked loop (90') is proportional to the average rate at which timing cells are received at the receive-end. In this manner the signal which reads the data out of the buffer (82) at the receive-end approaches the service clock (76) at the source end.

Abstract: A clock recovery circuit serves to recover a clock signal from data which does not arrive at predetermined times and which may be bursty. The clock recovery circuit operates in conjunction with a buffer which receives the data. Illustratively, the clock recovery circuit maintains a first count of the bytes of data written into the buffer and a second count of the byte of data transferred from the buffer. A subtractor substracts the second count from the first and a decision circuit utilizes the result to provide a signal indicative of the current occupancy of the buffer. Depending on the current occupancy, the frequency of an output signal of the clock recovery circuit is increased, decreased, or maintained as constant. This output signal thus serves as the recovered clock signal.