Patents by Inventor Cesar Aaron Ramirez

Cesar Aaron Ramirez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190094939
    Abstract: A method and apparatus is disclosed for minimizing power virus in a network on chip. The method includes an operational metric related to a node with at least one threshold, the node configured to manage communication of a first number of outbound transactions; determining, based on the comparison, a second number of outbound transactions from the first number of outbound transactions that are allowed from the node; and communicating the second number of outbound transactions. An apparatus for minimizing power virus in a network on chip is also disclosed.
    Type: Application
    Filed: September 22, 2017
    Publication date: March 28, 2019
    Inventors: Hans Yeager, Thomas Basnight, Zainab Nasreen Zaidi, Cesar Aaron Ramirez
  • Patent number: 9990291
    Abstract: Aspects disclosed herein include avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols. In this regard, an interface bridge circuit is communicatively coupled to a first core device that implements a retry bus coherency protocol, and a second core device that implements an in-order-response non-retry bus coherency protocol. The interface bridge circuit receives a snoop command from the first core device, and forwards the snoop command to the second core device. While the snoop command is pending, the interface bridge circuit detects a potential deadlock condition between the first core device and the second core device. In response to detecting the potential deadlock condition, the interface bridge circuit is configured to send a retry response to the first core device. This enables the first core device to continue processing, thereby eliminating the potential deadlock condition.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: June 5, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Hien Minh Le, Thuong Quang Truong, Kun Xu, Jaya Prakash Subramaniam Ganasan, Cesar Aaron Ramirez
  • Patent number: 9921962
    Abstract: Maintaining cache coherency using conditional intervention among multiple master devices is disclosed. In one aspect, a conditional intervention circuit is configured to receive intervention responses from multiple snooping master devices. To select a snooping master device to provide intervention data, the conditional intervention circuit determines how many snooping master devices have a cache line granule size the same as or larger than a requesting master device. If one snooping master device has a same or larger cache line granule size, that snooping master device is selected. If more than one snooping master device has a same or larger cache line granule size, a snooping master device is selected based on an alternate criteria. The intervention responses provided by the unselected snooping master devices are canceled by the conditional intervention circuit, and intervention data from the selected snooping master device is provided to the requesting master device.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: March 20, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Kun Xu, Thuong Quang Truong, Jaya Prakash Subramaniam Ganasan, Hien Minh Le, Cesar Aaron Ramirez
  • Publication number: 20170091098
    Abstract: Aspects disclosed herein include avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols. In this regard, an interface bridge circuit is communicatively coupled to a first core device that implements a retry bus coherency protocol, and a second core device that implements an in-order-response non-retry bus coherency protocol. The interface bridge circuit receives a snoop command from the first core device, and forwards the snoop command to the second core device. While the snoop command is pending, the interface bridge circuit detects a potential deadlock condition between the first core device and the second core device. In response to detecting the potential deadlock condition, the interface bridge circuit is configured to send a retry response to the first core device. This enables the first core device to continue processing, thereby eliminating the potential deadlock condition.
    Type: Application
    Filed: September 24, 2015
    Publication date: March 30, 2017
    Inventors: Hien Minh Le, Thuong Quang Truong, Kun Xu, Jaya Prakash Subramaniam Ganasan, Cesar Aaron Ramirez
  • Publication number: 20170091095
    Abstract: Maintaining cache coherency using conditional intervention among multiple master devices is disclosed. In one aspect, a conditional intervention circuit is configured to receive intervention responses from multiple snooping master devices. To select a snooping master device to provide intervention data, the conditional intervention circuit determines how many snooping master devices have a cache line granule size the same as or larger than a requesting master device. If one snooping master device has a same or larger cache line granule size, that snooping master device is selected. If more than one snooping master device has a same or larger cache line granule size, a snooping master device is selected based on an alternate criteria. The intervention responses provided by the unselected snooping master devices are canceled by the conditional intervention circuit, and intervention data from the selected snooping master device is provided to the requesting master device.
    Type: Application
    Filed: September 24, 2015
    Publication date: March 30, 2017
    Inventors: Kun Xu, Thuong Quang Truong, Jaya Prakash Subramaniam Ganasan, Hien Minh Le, Cesar Aaron Ramirez