Abstract: The disclosure relates to a semiconductor device having a first active region, a plurality of elongated gate regions having an elongated extension in a first lateral direction, respectively, a plurality of elongated field plate regions having an elongated extension in the first lateral direction, respectively, and a first additional gate region, wherein a first one of the elongated gate regions is arranged in a first elongated gate trench at a first side of the first active region, and a second one of the elongated gate regions is arranged in a second elongated gate trench at a second side of the first active region, the second side lying opposite to the first side with respect to a second lateral direction, and wherein the first additional gate region is arranged in a first additional gate trench which extends at least proportionately in the second lateral direction through the first active region.

Abstract: In an embodiment, a transistor device comprises a semiconductor body comprising a plurality of transistor cells comprising a drift region of a first conductivity type, a body region of a second conductivity type forming a first pn junction with the drift region, the second conductivity type opposing the first conductivity type, a source region of the first conductivity type forming a second pn junction with the body region, a columnar field plate trench extending into a major surface of a semiconductor body and comprising a columnar field plate and a gate trench structure extending into the major surface of the semiconductor body and comprising a gate electrode. At least one of the depth and doping level of the body region locally varies within the transistor cell to improve VGSTH homogeneity within the transistor cell.

Abstract: A semiconductor device includes a semiconductor body having an active area with active transistor cells. Each active transistor cell includes a columnar trench having a field plate and a mesa. An edge termination region that laterally surrounds the active area includes a transition region, an outer termination region, and inactive cells arranged in the transition region and outer termination region. Each inactive cell includes a columnar termination trench having a field plate and a termination mesa including a drift region. In the transition region, the termination mesa includes a body region arranged on the drift region and in the outer termination region the drift region of the termination mesa extends to the first surface. The edge termination region further includes a continuous trench positioned in the outer termination region, that laterally surrounds the columnar termination trenches, and is filled with at least one dielectric material.

Abstract: The disclosure relates to a semiconductor device having a first active region, a plurality of elongated gate regions having an elongated extension in a first lateral direction, respectively, a plurality of elongated field plate regions having an elongated extension in the first lateral direction, respectively, and a first additional gate region, wherein a first one of the elongated gate regions is arranged in a first elongated gate trench at a first side of the first active region, and a second one of the elongated gate regions is arranged in a second elongated gate trench at a second side of the first active region, the second side lying opposite to the first side with respect to a second lateral direction, and wherein the first additional gate region is arranged in a first additional gate trench which extends at least proportionately in the second lateral direction through the first active region.

Abstract: A transistor device includes, in a semiconductor body, a drift region, a body region, and a source region separated from the drift region by the body region and connected to a source node. The transistor device further includes a gate electrode dielectrically insulated from the body region by a gate dielectric, and a field electrode structure. The field electrode structure includes: a first field electrode connected to the source node and dielectrically insulated from the drift region by a first field electrode dielectric; a second field electrode dielectrically insulated from the drift region by a second field electrode dielectric; and a coupling circuit connected between the second field electrode and the source node and configured to connect the second field electrode to the source node dependent on a voltage between the source node and the second field electrode.

Abstract: Disclosed is a transistor device with at least one gate electrode, a gate runner connected to the at least one gate electrode and arranged on top of a semiconductor body, and a gate pad arranged on top of the semiconductor body and electrically connected to the gate runner. The gate runner includes a first metal line, a second metal line on top of the first metal line, a first gate runner section, and at least one second gate runner section. The at least one second gate runner section is arranged between the first gate runner section and the gate pad. A cross sectional area of the second metal line in the at least one second gate runner section is less than 50% of the cross sectional area of the second metal line in the first gate runner section.

Abstract: Techniques are provided for avoiding an avalanche breakdown voltage across a synchronous rectification (SR) switch on the secondary side of an isolated switched-mode power converter operating in a low-power mode, e.g., a burst mode, during which a load of the power converter draws negligible current. This is accomplished via use of a two-level switch driver for controlling a power switch on the primary side of the power converter. The two-level switch driver is configured to source low current levels to a control terminal (e.g., gate) of the power switch during burst-mode operation. This low current reduces the slope of the rising edge of voltage pulses on the primary and secondary sides of the power converter which, in turn, limits the peak of the voltage ringing across the SR switch. By limiting the voltage in this manner, the SR switch avoids entering avalanche breakdown.

Abstract: Techniques are provided for avoiding an avalanche breakdown voltage across a synchronous rectification (SR) switch on the secondary side of an isolated switched-mode power converter operating in a low-power mode, e.g., a burst mode, during which a load of the power converter draws negligible current. This is accomplished via use of a two-level switch driver for controlling a power switch on the primary side of the power converter. The two-level switch driver is configured to source low current levels to a control terminal (e.g., gate) of the power switch during burst-mode operation. This low current reduces the slope of the rising edge of voltage pulses on the primary and secondary sides of the power converter which, in turn, limits the peak of the voltage ringing across the SR switch. By limiting the voltage in this manner, the SR switch avoids entering avalanche breakdown.

Abstract: A power semiconductor device includes a semiconductor substrate having a first side. A plurality of active transistor cells is formed in an active area of the semiconductor substrate. Each of the plurality of active transistor cells includes a spicular trench which extends from the first side into the semiconductor substrate and has a field electrode. A gate electrode structure has a plurality of intersecting gate trenches running between the spicular trenches. The intersecting gate trenches form gate crossing regions of different shape when seen in a plan projection onto the first side of the power semiconductor device.

Abstract: A transistor device includes, in a semiconductor body, a drift region, a body region, and a source region separated from the drift region by the body region and connected to a source node. The transistor device further includes a gate electrode dielectrically insulated from the body region by a gate dielectric, and a field electrode structure. The field electrode structure includes: a first field electrode connected to the source node and dielectrically insulated from the drift region by a first field electrode dielectric; a second field electrode dielectrically insulated from the drift region by a second field electrode dielectric; and a coupling circuit connected between the second field electrode and the source node and configured to connect the second field electrode to the source node dependent on a voltage between the source node and the second field electrode.

Abstract: A vertical semiconductor field-effect transistor includes a semiconductor body having a front side, and a field electrode trench extending from the front side into the semiconductor body. The field electrode trench includes a field electrode and a field dielectric arranged between the field electrode and the semiconductor body. The vertical semiconductor field-effect transistor further includes a gate electrode trench arranged next to the field electrode trench, extending from the front side into the semiconductor body, and having two electrodes which are separated from each other and the semiconductor body. A front side metallization is arranged on the front side and in contact with the field electrode and at most one of the two electrodes.

Abstract: Disclosed is a transistor device with at least one gate electrode, a gate runner connected to the at least one gate electrode and arranged on top of a semiconductor body, and a gate pad arranged on top of the semiconductor body and electrically connected to the gate runner. The gate runner includes a first metal line, a second metal line on top of the first metal line, a first gate runner section, and at least one second gate runner section. The at least one second gate runner section is arranged between the first gate runner section and the gate pad. A cross sectional area of the second metal line in the at least one second gate runner section is less than 50% of the cross sectional area of the second metal line in the first gate runner section.

Abstract: A power semiconductor device includes a semiconductor substrate having a first side. A plurality of active transistor cells is formed in an active area of the semiconductor substrate. Each of the plurality of active transistor cells includes a spicular trench which extends from the first side into the semiconductor substrate and has a field electrode. A gate electrode structure has a plurality of intersecting gate trenches running between the spicular trenches. The intersecting gate trenches form gate crossing regions of different shape when seen in a plan projection onto the first side of the power semiconductor device.

Abstract: A vertical semiconductor field-effect transistor includes a semiconductor body having a front side, and a field electrode trench extending from the front side into the semiconductor body The field electrode trench includes a field electrode and a field dielectric arranged between the field electrode and the semiconductor body. The vertical semiconductor field-effect transistor further includes a gate electrode trench arranged next to the field electrode trench, extending from the front side into the semiconductor body, and having two electrodes which are separated from each other and the semiconductor body. A front side metallization is arranged on the front side and in contact with the field electrode and at most one of the two electrodes.

Abstract: A synchronous rectifier is described that includes a transistor device that has a gate terminal, a source terminal, a drain terminal, and a field-plate electrode. The field-plate electrode of the transistor device includes an integrated diode. The integrated diode is configured to discharge a parasitic capacitance of the transistor device during each switching operation of the synchronous rectifier. In some examples, the integrated diode is also configured to charge the parasitic capacitance of the transistor device during each switching operation of the synchronous rectifier.

Abstract: Embodiments of the present invention describe a voltage converter and a method for operating the voltage converter. In one embodiment the voltage converter includes a primary path configured to generate a pulse modulated voltage or current from an input direct current (DC) voltage, a transformer arrangement with m?1 primary windings and n?2 secondary windings inductively coupled together, the m primary windings being connected to the primary path, and a secondary path configured to output a pulsed direct current (DC) voltage or current, wherein the secondary path includes n capacitors connected in series and n secondary controllable semiconductor switches, and each of the n secondary windings is connected via at least one of the secondary controllable semiconductor switches to at least one of the capacitors.

Abstract: A synchronous rectifier is described that includes a transistor device that has a gate terminal, a source terminal, a drain terminal, and a field-plate electrode. The field-plate electrode of the transistor device includes an integrated diode. The integrated diode is configured to discharge a parasitic capacitance of the transistor device during each switching operation of the synchronous rectifier. In some examples, the integrated diode is also configured to charge the parasitic capacitance of the transistor device during each switching operation of the synchronous rectifier.

Abstract: Embodiments of the present invention describe a voltage converter and a method for operating the voltage converter. In one embodiment the voltage converter includes a primary path configured to generate a pulse modulated voltage or current from an input direct current (DC) voltage, a transformer arrangement with m?1 primary windings and n?2 secondary windings inductively coupled together, the m primary windings being connected to the primary path, and a secondary path configured to output a pulsed direct current (DC) voltage or current, wherein the secondary path includes n capacitors connected in series and n secondary controllable semiconductor switches, and each of the n secondary windings is connected via at least one of the secondary controllable semiconductor switches to at least one of the capacitors.

Abstract: Embodiments of the present invention describe a voltage converter and a method for operating the voltage converter. In one embodiment the voltage converter includes a primary path configured to generate a pulse modulated voltage or current from an input direct current (DC) voltage, a transformer arrangement with m?1 primary windings and n?2 secondary windings inductively coupled together, the m primary windings being connected to the primary path, and a secondary path configured to output a pulsed direct current (DC) voltage or current, wherein the secondary path includes n capacitors connected in series and n secondary controllable semiconductor switches, and each of the n secondary windings is connected via at least one of the secondary controllable semiconductor switches to at least one of the capacitors.