Abstract: A digital frequency synthesizer employs a predetermined residue number system to generate phase angle information. The phase angle information is then converted from the predetermined residue number system into a weighted binary number. A part of the weighted binary phase angle information is used to address a read only memory that includes predetermined initial data points at each address. A predetermined iteration process that makes use of some or all of the weighted binary phase angle information that was not used to address the read only memory is then employed in an iterative process to generate final data points for the predetermined waveform. The initial data points are stored in the read only memory as weighted binary numbers and the iterative process employs weighted binary arithmetic. A second embodiment stores the initial data points in the read only memory as digits from a predetermined residue number system and the iterative process employs residue number system arithmetic.

Abstract: An asynchronous data input signal is detected and synchronized by a fast-acting circuit. The input is used to modulate a local clock and a detecting latch is then driven by the data-modulated clock. Most of the propagation delay found in conventional detector-synchronizers is eliminated since the SET input to the latch, which is essentially the clock signal, is generated without any gate delay and the CLEAR input is generated with only a single gate delay. Thus, the circuit is well suited for multiple clock systems in which detection and synchronization to one clock must be accomplished before the pulse of a second clock begins.

Abstract: The output of a fast-acting ratioless logic circuit is monitored by a sensing device, and when one selected logic output is sensed, a voltage is applied to the output node to latch the output to that state. To effect rapid return to the other state, a switch is provided to deactivate the applied voltage when the output node is established at the other state. The latching is made permanent by the further application of a refresh clock which periodically pulses the output node whenever the one selected state is latched.

Abstract: A two phase clock signal with separation between the two phases is produced from a single phase clock. Two complementary input signals are derived from the single phase clock and are transferred by separate transfer gates to individual push/pull amplifiers. Each gated input signal is applied to the first input of one of the amplifiers while the complementary input signals are connected directly to the second input of the amplifiers. The output of each push/pull amplifier is one of the clock phases, and each is also applied to a sensing circuit. The sensing circuit produces delayed outputs which are cross-coupled to control the transfer gate associated with the other output phase. By judicious selection of the parameters of the sensing circuit, the time and speed of "turn-on" for each transfer gate can be controlled. Accordingly, the separation between the two clock phases as well as the shape of each can be selected.